Datasheet

ManualsBrandsMICROCHIP TECHNOLOGY ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller SOIC 18 8-Bit 20 MHz I/O number 16

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Table Of Contents

High Performance RISC CPU:
Special Microcontroller Features:
Low Power Features:
Peripheral Features:
Pin Diagrams
Most Current Data Sheet
Errata
Customer Notification System
1.0 General Description
- TABLE 1-1: PIC16F627A/628A/648A Family of Devices
2.0 PIC16F627A/628A/648A Device Varieties
3.0 Architectural Overview
- TABLE 3-1: Device MEMORY LIST
- FIGURE 3-1: BLOCK DIAGRAM
- TABLE 3-2: PIC16F627A/628A/648A Pinout Description
- FIGURE 3-2: CLOCK/INSTRUCTION CYCLE
4.0 Memory Organization
- FIGURE 4-1: Program Memory Map and Stack
- TABLE 4-1: general purpose STATIC ram Registers
- TABLE 4-2: Access to Banks of Registers
- FIGURE 4-2: Data Memory Map of the PIC16F627A and PIC16F628A
- FIGURE 4-3: Data Memory Map of the PIC16F648A
- TABLE 4-3: Special Registers Summary Bank0
- TABLE 4-4: Special Function Registers Summary Bank1
- TABLE 4-5: Special Function Registers Summary Bank2
- TABLE 4-6: Special Function Registers Summary Bank3
- FIGURE 4-4: Loading Of PC In Different Situations
- FIGURE 4-5: Direct/Indirect Addressing PIC16F627A/628A/648A
5.0 I/O Ports
- FIGURE 5-1: Block Diagram of RA0/AN0:RA1/AN1 Pins
- FIGURE 5-2: Block Diagram of RA2/Vref Pin
- FIGURE 5-3: Block Diagram of the RA3/AN3 Pin
- FIGURE 5-4: Block Diagram of RA4/T0CKI Pin
- FIGURE 5-5: Block Diagram of the RA5/MCLR/Vpp Pin
- FIGURE 5-6: Block Diagram of RA6/OSC2/CLKOUT Pin
- FIGURE 5-7: Block Diagram of RA7/OSC1/CLKIN Pin
- TABLE 5-1: PORTA Functions
- TABLE 5-2: Summary of Registers Associated with PORTA(1)
- FIGURE 5-8: Block Diagram of RB0/INT Pin
- FIGURE 5-9: Block Diagram of RB1/RX/DT Pin
- FIGURE 5-10: Block Diagram of RB2/TX/CK Pin
- FIGURE 5-11: Block Diagram of RB3/CCP1 Pin
- FIGURE 5-12: Block Diagram of RB4/PGM Pin
- FIGURE 5-13: Block Diagram of RB5 Pin
- FIGURE 5-14: Block Diagram of RB6/T1OSO/T1CKI Pin
- FIGURE 5-15: Block Diagram of the RB7/T1OSI Pin
- TABLE 5-3: PORTB Functions
- TABLE 5-4: Summary of Registers Associated With PORTB(1)
- FIGURE 5-16: Successive I/O Operation
6.0 Timer0 Module
- FIGURE 6-1: Block Diagram of thE Timer0/WDT
- TABLE 6-1: Registers Associated with Timer0
7.0 Timer1 Module
- FIGURE 7-1: Timer1 Block Diagram
- TABLE 7-1: Capacitor Selection for the Timer1 Oscillator
- TABLE 7-2: Registers Associated with Timer1 as a Timer/Counter
8.0 Timer2 Module
- FIGURE 8-1: Timer2 Block Diagram
- TABLE 8-1: Registers Associated with Timer2 as a Timer/Counter
9.0 Capture/Compare/PWM (CCP) Module
- TABLE 9-1: CCP Mode - Timer Resource
- FIGURE 9-1: Capture Mode Operation Block Diagram
- FIGURE 9-2: Compare Mode Operation Block Diagram
- TABLE 9-2: Registers Associated with Capture, compare, and Timer1
- FIGURE 9-3: Simplified PWM Block Diagram
- FIGURE 9-4: PWM OUTPUT
- TABLE 9-3: Example PWM Frequencies and Resolutions at 20 MHz
- TABLE 9-4: Registers Associated with PWM and Timer2
10.0 Comparator Module
- FIGURE 10-1: Comparator I/O Operating Modes
- FIGURE 10-2: Single Comparator
- FIGURE 10-3: Modified Comparator Output Block Diagram
- FIGURE 10-4: Analog Input Mode
- TABLE 10-1: Registers Associated with Comparator Module
11.0 Voltage Reference Module
- FIGURE 11-1: Voltage Reference Block Diagram
- FIGURE 11-2: Voltage Reference Output Buffer Example
- TABLE 11-1: Registers Associated with Voltage Reference
12.0 Universal Synchronous Asynchronous Receiver Transmitter (USART) Module
- TABLE 12-1: BAUD rATE fORMULA
- TABLE 12-2: Registers Associated with Baud Rate Generator
- TABLE 12-3: Baud Rates for synchronous Mode
- TABLE 12-4: Baud Rates for Asynchronous Mode (BRGH = 0)
- TABLE 12-5: Baud Rates for Asynchronous Mode (BRGH = 1)
- FIGURE 12-1: RX Pin Sampling Scheme. BRGH = 0
- FIGURE 12-2: RX Pin Sampling Scheme, BRGH = 1
- FIGURE 12-3: RX Pin Sampling Scheme, BRGH = 1
- FIGURE 12-4: RX Pin Sampling Scheme, BRGH = 0 OR BRGH = 1
- FIGURE 12-5: USART Transmit Block Diagram
- FIGURE 12-6: Asynchronous Transmission
- FIGURE 12-7: Asynchronous Transmission (Back to Back)
- TABLE 12-6: Registers Associated with Asynchronous Transmission
- FIGURE 12-8: USART Receive Block Diagram
- FIGURE 12-9: Asynchronous Reception with Address Detect
- FIGURE 12-10: Asynchronous Reception with Address Byte First
- FIGURE 12-11: Asynchronous Reception with Address Byte First Followed by Valid Data Byte
- TABLE 12-7: Registers Associated with Asynchronous Reception
- TABLE 12-8: Registers Associated with Asynchronous Reception
- TABLE 12-9: Registers Associated with Synchronous Master Transmission
- FIGURE 12-12: Synchronous Transmission
- FIGURE 12-13: Synchronous Transmission (Through TXEN)
- TABLE 12-10: Registers Associated with Synchronous Master Reception
- FIGURE 12-14: Synchronous Reception (Master Mode, SREN)
- TABLE 12-11: Registers Associated with Synchronous Slave Transmission
- TABLE 12-12: Registers Associated with Synchronous Slave Reception
13.0 Data EEPROM Memory
- TABLE 13-1: Registers/Bits Associated with Data EEPROM
14.0 Special Features of the CPU
- FIGURE 14-1: Crystal Operation (or Ceramic Resonator) (HS, XT or LP Osc Configuration)
- TABLE 14-1: Capacitor Selection for Ceramic Resonators
- TABLE 14-2: Capacitor Selection for Crystal Oscillator
- FIGURE 14-2: External Parallel Resonant Crystal Oscillator Circuit
- FIGURE 14-3: External Series Resonant Crystal Oscillator Circuit
- FIGURE 14-4: External Clock Input Operation (EC, HS, XT or LP Osc Configuration)
- FIGURE 14-5: RC OSCILLATOR MODE
- FIGURE 14-6: Simplified Block Diagram of On-chip Reset Circuit
- FIGURE 14-7: Brown-out Situations WITH PWRT ENABLED
- TABLE 14-3: Time out in Various Situations
- TABLE 14-4: Status/PCON Bits and Their Significance
- TABLE 14-5: Summary of Registers Associated with Brown-out Reset
- TABLE 14-6: Initialization Condition for Special Registers
- TABLE 14-7: Initialization Condition for Registers
- FIGURE 14-8: Time out Sequence on Power-up (MCLR not tied to Vdd): Case
- FIGURE 14-9: Time out Sequence on Power-up (MCLR not tied to Vdd): Case 2
- FIGURE 14-10: Time out Sequence on Power-up (MCLR tied to Vdd)
- FIGURE 14-11: External Power-on Reset Circuit (For Slow Vdd Power-up)
- FIGURE 14-12: External Brown-out Protection Circuit 1
- FIGURE 14-13: External Brown-out Protection Circuit 2
- FIGURE 14-14: Interrupt Logic
- FIGURE 14-15: INT Pin Interrupt Timing
- TABLE 14-8: Summary of interrupt registers
- FIGURE 14-16: Watchdog Timer Block Diagram
- TABLE 14-9: Summary of Watchdog Timer Registers
- FIGURE 14-17: Wake-up from Sleep Through Interrupt
- FIGURE 14-18: Typical In-Circuit Serial Programming Connection
15.0 Instruction Set Summary
- TABLE 15-1: OPCODE Field Descriptions
- FIGURE 15-1: General Format for Instructions
- TABLE 15-2: PIC16F627A/628A/648A Instruction SeT
16.0 Development Support
- TABLE 16-1: DEVELOPMENT TOOLS FROM MICROCHIP
17.0 Electrical Specifications
- FIGURE 17-1: PIC16F627A/628A/648A VOLTAGE-FREQUENCY GRAPH, -40°C £ TA £ +125°C
- FIGURE 17-2: PIC16LF627A/628A/648A VOLTAGE-FREQUENCY GRAPH, -40°C £ TA £ +85°C
- TABLE 17-1: DC Characteristics: PIC16F627A/628A/648A (Industrial, Extended) PIC16LF627A/628A/648A...
- TABLE 17-2: Comparator Specifications
- TABLE 17-3: Voltage Reference Specifications
- FIGURE 17-3: Load Conditions
- FIGURE 17-4: External Clock Timing
- TABLE 17-4: External Clock Timing Requirements
- TABLE 17-5: pRECISION INTERNAL OSCILLATOR Parameters
- FIGURE 17-5: CLKOUT and I/O Timing
- TABLE 17-6: CLKOUT and I/O Timing Requirements
- FIGURE 17-6: Reset, Watchdog Timer, Oscillator Start-Up Timer and Power-Up Timer Timing
- FIGURE 17-7: Brown-out Detect Timing
- TABLE 17-7: Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Requirements
- FIGURE 17-8: Timer0 and Timer1 External Clock Timings
- TABLE 17-9: Timer0 and Timer1 External Clock Requirements
- FIGURE 17-10: Capture/Compare/PWM Timings
- TABLE 17-8: Capture/Compare/PWM Requirements
- FIGURE 17-11: TIMER0 Clock Timing
- TABLE 17-9: TIMER0 Clock Requirements
18.0 DC and AC Characteristics Graphs and Tables
19.0 Packaging Information
Appendix A: Data Sheet Revision History
- Revision A
Appendix B: Device Differences
Appendix C: Device Migrations
Appendix D: Migrating from other PICmicro Devices
Appendix E: Development Tool Version Requirements
- On-Line Support
  - Connecting to the Microchip Internet Web Site
- Systems Information and Upgrade Hot Line
- Reader Response
Index
- A
- B
- C
- D
- E
- G
- I
- K
- M
- N
- O
- P
- Q
- R
- S
- T
- U
- V
- W
- X
- Product Identification System
Product ID System
Worldwide Sales

 2002 Microchip Technology Inc. Preliminary DS40044A-page 161

PIC16F627A/628A/648A

INDEX

A/D

Special Event Trigger (CCP)....................................... 57

Absolute Maximum Ratings .............................................. 131

ADDLW Instruction ........................................................... 113

ADDWF Instruction ........................................................... 113

ANDLW Instruction ........................................................... 113

ANDWF Instruction ........................................................... 113

Architectural Overview .......................................................... 9

Assembler

MPASM Assembler ................................................... 125

Baud Rate Error .................................................................. 71

Baud Rate Formula............................................................. 71

BCF Instruction ................................................................. 114

Block Diagrams

Comparator

I/O Operating Modes .......................................... 62

Modified Comparator Output .............................. 64

I/O Ports

RB0/INT Pin........................................................ 37

RB1/RX/DT Pin................................................... 37

RB2/TX/CK Pin ................................................... 38

RB3/CCP1 Pin .................................................... 38

RB4/PGM Pin ..................................................... 39

RB5 Pin............................................................... 40

RB6/T1OSO/T1CKI Pin ...................................... 41

RB7/T1OSI Pin ................................................... 42

RC Oscillator Mode..................................................... 96

USART Receive.......................................................... 79

USART Transmit ......................................................... 77

BRGH bit............................................................................. 71

Brown-Out Reset (BOR) ..................................................... 98

BSF Instruction ................................................................. 114

BTFSC Instruction............................................................. 114

BTFSS Instruction............................................................. 115

CALL Instruction ............................................................... 115

Capture (CCP Module) ....................................................... 56

Block Diagram............................................................. 56

CCP Pin Configuration................................................ 56

CCPR1H:CCPR1L Registers...................................... 56

Changing Between Capture Prescalers...................... 56

Prescaler..................................................................... 56

Software Interrupt ....................................................... 56

Timer1 Mode Selection ............................................... 56

Capture/Compare/PWM (CCP)........................................... 55

Capture Mode. See Capture

CCP1 .......................................................................... 55

CCPR1H Register............................................... 55

CCPR1L Register ............................................... 55

CCP2 .......................................................................... 55

Compare Mode. See Compare

PWM Mode. See PWM

Timer Resources......................................................... 55

CCP1CON Register

CCP1M3:CCP1M0 Bits............................................... 55

CCP1X:CCP1Y Bits .................................................... 55

CCP2CON Register

CCP2M3:CCP2M0 Bits............................................... 55

CCP2X:CCP2Y Bits .................................................... 55

Clocking Scheme/Instruction Cycle .................................... 13

CLRF Instruction............................................................... 115

CLRW Instruction.............................................................. 116

CLRWDT Instruction......................................................... 116

Code Examples

Data EEPROM Refresh Routine ................................ 92

Code Protection................................................................ 108

COMF Instruction.............................................................. 116

Comparator

Block Diagrams

I/O Operating Modes .......................................... 62

Modified Comparator Output .............................. 64

Comparator Module.................................................... 61

Configuration .............................................................. 62

Interrupts .................................................................... 65

Operation.................................................................... 63

Reference ................................................................... 63

Compare (CCP Module) ..................................................... 56

Block Diagram ............................................................ 56

CCP Pin Configuration ............................................... 57

CCPR1H:CCPR1L Registers ..................................... 56

Software Interrupt ....................................................... 57

Special Event Trigger ................................................. 57

Timer1 Mode Selection............................................... 57

Configuration Bits ............................................................... 93

Crystal Operation................................................................ 95

Data EEPROM Memory...................................................... 89

EECON1 Register ...................................................... 89

EECON2 Register ...................................................... 89

Operation During Code Protection ............................. 92

Reading ...................................................................... 91

Spurious Write Protection........................................... 91

Using .......................................................................... 92

Write Verify ................................................................. 91

Writing to .................................................................... 91

Data Memory Organization................................................. 15

DECF Instruction .............................................................. 116

DECFSZ Instruction.......................................................... 117

Development Support....................................................... 125

Development Tool Version Requirements........................ 157

Device Differences............................................................ 155

Device Migrations ............................................................. 156

Dual-speed Oscillator Modes.............................................. 97

EECON1 register................................................................ 90

EECON2 register................................................................ 90

Errata.................................................................................... 3

External Crystal Oscillator Circuit ....................................... 95

General-Purpose Register File ........................................... 15

GOTO Instruction.............................................................. 117

I/O Ports ............................................................................. 31

Bi-Directional .............................................................. 44

Block Diagrams

RB0/INT Pin........................................................ 37

RB1/RX/DT Pin................................................... 37

RB2/TX/CK Pin................................................... 38

RB3/CCP1 Pin.................................................... 38

RB4/PGM Pin ..................................................... 39