Datasheet

PIC16F62X
DS40300C-page 76 Preliminary  2003 Microchip Technology Inc.
FIGURE 12-7: ASYNCHRONOUS TRANSMISSION (BACK TO BACK)
TABLE 12-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR
Value on
all other
RESETS
0Ch PIR1
EEIF CMIF RCIF TXIF — CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000
18h RCSTA
SPEN RX9 SREN CREN ADEN FERR OERR RX9D 0000 -00x 0000 -00x
19h TXREG
USART Transmit Register 0000 0000 0000 0000
8Ch PIE1
EEIE CMIE RCIE TXIE — CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000
98h TXSTA
CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, - = unimplemented locations read as '0'.
Shaded cells are not used for Asynchronous Transmission.
Transmit Shift Reg.
Write to TXREG
BRG output
(shift clock)
RB2/TX/CK (pin)
TXIF bit
(interrupt reg. flag)
TRMT bit
(Transmit shift
reg. empty flag)
WORD 1
WORD 2
WORD 1
WORD 2
START Bit
STOP Bit
START Bit
Transmit Shift Reg.
WORD 1
WORD 2
Bit 0 Bit 1
Bit 7/8 Bit 0
.
Note 1: This timing diagram shows two consecutive transmissions.