Datasheet

PIC16F62X
DS40300C-page 36 Preliminary  2003 Microchip Technology Inc.
FIGURE 5-10: BLOCK DIAGRAM OF
RB2/TX/CK PIN
FIGURE 5-11: BLOCK DIAGRAM OF
RB3/CCP1 PIN
Data Latch
TRIS Latch
RD TRISB
Q
D
Q
CK
Q
D
Q
CK
0
1
WR PORTB
WR TRISB
Schmitt
Trigger
Peripheral OE
(2)
Data Bus
PORT/PERIPHERAL
Select
(1)
USART TX/CK Output
USART Slave Clock In
RBPU
VDD
P
EN
QD
VDD
VSS
Note 1: Port/Peripheral select signal selects between port
data and peripheral output.
2: Peripheral OE
(output enable) is only active if
peripheral select is active.
RD PORTB
TTL
Input
Buffer
RB2/
TX/CK
Weak
Pull-up
Data Latch
TRIS Latch
RD TRISB
Q
D
Q
CK
Q
D
Q
CK
0
1
WR PORTB
WR TRISB
Schmitt
Trigger
Peripheral OE
(2)
Data Bus
PORT/PERIPHERAL
Select
(1)
USART TX/CK output
USART Slave Clock In
RBPU
VDD
P
EN
QD
VDD
VSS
Note 1: Port/Peripheral select signal selects between port
data and peripheral output.
2: Peripheral OE
(output enable) is only active if
peripheral select is active.
RD PORTB
TTL
Input
Buffer
RB3/
CCP1
Weak
Pull-up