Datasheet

PIC16F62X
DS40300C-page 30 Preliminary  2003 Microchip Technology Inc.
FIGURE 5-1: BLOCK DIAGRAM OF
RA0/AN0:RA1/AN1 PINS
FIGURE 5-2: BLOCK DIAGRAM OF
RA2/VREF PIN
FIGURE 5-3: BLOCK DIAGRAM OF THE RA3/AN3 PIN
Data
Bus
QD
Q
CK
WR
PORTA
WR
TRISA
Data Latch
TRIS Latch
RD
RD PORTA
Analog
I/O Pin
QD
Q
CK
Input Mode
DQ
EN
To Comparator
Schmitt Trigger
Input Buffer
VDD
VSS
TRISA
Data
Bus
QD
Q
CK
WR
PORTA
WR
TRISA
Data Latch
TRIS Latch
RD
RD PORTA
Analog
RA2 Pin
QD
Q
CK
Input Mode
DQ
EN
To Comparator
Schmitt Trigger
Input Buffer
VROE
VREF
VDD
VSS
TRISA
Data
Bus
QD
Q
CK
WR
PORTA
WR
TRISA
Data Latch
TRIS Latch
RD
RD PORTA
Analog
RA3 Pin
QD
Q
CK
DQ
EN
To Comparator
Schmitt Trigger
Input Buffer
Input Mode
Comparator Output
Comparator Mode = 110
1
0
VDD
VSS
TRISA