PIC16F62X Data Sheet FLASH-Based 8-Bit CMOS Microcontroller 2003 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
PIC16F62X FLASH-Based 8-Bit CMOS Microcontrollers Devices Included in this Data Sheet: • Universal Synchronous/Asynchronous Receiver/ Transmitter USART/SCI • 16 Bytes of common RAM • PIC16F627 • PIC16F628 Referred to collectively as PIC16F62X Special Microcontroller Features: High Performance RISC CPU: • Power-on Reset (POR) • Power-up Timer (PWRT) and Oscillator Start-up Timer (OST) • Brown-out Detect (BOD) • Watchdog Timer (WDT) with its own on-chip RC oscillator for reliable operation • Multiplexed
PIC16F62X Pin Diagrams PDIP, SOIC RA5/MCLR/VPP VSS RB0/INT RB1/RX/DT RB2/TX/CK RB3/CCP1 •1 2 3 4 5 6 7 8 9 PIC16F62X RA2/AN2/VREF RA3/AN3/CMP1 RA4/TOCKI/CMP2 18 17 16 15 14 13 12 11 10 RA1/AN1 RA0/AN0 RA7/OSC1/CLKIN RA6/OSC2/CLKOUT VDD RB7/T1OSI/PGD RB6/T1OSO/T1CKI/PGC RB5 RB4/PGM 20 19 18 17 16 15 14 13 12 11 RA1/AN1 SSOP RA2/AN2/VREF RB1/RX/DT RB2/TX/CK RB3/CCP1 •1 2 3 4 5 6 7 8 9 10 PIC16F62X RA3/AN3/CMP1 RA4/TOCKI/CMP2 RA5/MCLR/VPP VSS VSS RB0/INT RA0/AN0 RA7/OSC1/CLKIN RA6/OSC2/CLKOUT VDD
PIC16F62X Table of Contents 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 11.0 12.0 13.0 14.0 15.0 16.0 17.0 18.0 19.0 General Description...................................................................................................................................................................... 5 PIC16F62X Device Varieties........................................................................................................................................................ 7 Architectural Overview .....
PIC16F62X NOTES: DS40300C-page 4 Preliminary 2003 Microchip Technology Inc.
PIC16F62X 1.0 PIC16F62X DEVICE VARIETIES A variety of frequency ranges and packaging options are available. Depending on application and production requirements, the proper device option can be selected using the information in the PIC16F62X Product Identification System section (Page 167) at the end of this data sheet. When placing orders, please use this page of the data sheet to specify the correct part number. 1.1 FLASH Devices FLASH devices can be erased and reprogrammed electrically.
PIC16F62X NOTES: DS40300C-page 6 Preliminary 2003 Microchip Technology Inc.
PIC16F62X 2.0 ARCHITECTURAL OVERVIEW The high performance of the PIC16F62X family can be attributed to a number of architectural features commonly found in RISC microprocessors. To begin with, the PIC16F62X uses a Harvard architecture, in which, program and data are accessed from separate memories using separate buses. This improves bandwidth over traditional Von Neumann architecture where program and data are fetched from the same memory.
PIC16F62X FIGURE 2-1: BLOCK DIAGRAM 13 Program Memory RAM File Registers 8-Level Stack (13-bit) Program Bus 14 8 Data Bus Program Counter FLASH RAM Addr (1) PORTA 9 Addr MUX Instruction reg Direct Addr 7 8 RA0/AN0 RA1/AN1 RA2/AN2/VREF RA3/AN3/CMP1 RA4/T0CK1/CMP2 RA5/MCLR/VPP RA6/OSC2/CLKOUT RA7/OSC1/CLKIN Indirect Addr FSR reg STATUS reg 8 3 Power-up Timer Instruction Decode & Control Timing Generation OSC1/CLKIN OSC2/CLKOUT Oscillator Start-up Timer MUX RB0/INT RB1/RX/DT RB2/TX/CK RB
PIC16F62X TABLE 2-1: PIC16F62X PINOUT DESCRIPTION Name RA0/AN0 Function Input Type Output Type RA0 ST CMOS Description Bi-directional I/O port AN0 AN — RA1/AN1 RA1 ST CMOS AN1 AN — RA2/AN2/VREF RA2 ST CMOS AN2 AN — Analog comparator input VREF — AN VREF output RA3 ST CMOS AN3 AN — CMP1 — CMOS Comparator 1 output RA4 ST OD Bi-directional I/O port T0CKI ST — Timer0 clock input CMP2 — OD Comparator 2 output RA5 ST — Input port MCLR ST — Master clear
PIC16F62X TABLE 2-1: PIC16F62X PINOUT DESCRIPTION (CONTINUED) Name RB4/PGM Function Input Type Output Type Description RB4 TTL CMOS PGM ST — RB5 RB5 TTL CMOS Bi-directional I/O port. Interrupt-on-pin change. Can be software programmed for internal weak pull-up. RB6/T1OSO/T1CKI/PGC RB6 TTL CMOS Bi-directional I/O port. Interrupt-on-pin change. Can be software programmed for internal weak pull-up. T1OSO — XTAL Timer1 oscillator output. T1CKI ST — Timer1 clock input.
PIC16F62X 2.1 Clocking Scheme/Instruction Cycle 2.2 Instruction Flow/Pipelining An “Instruction Cycle” consists of four Q cycles (Q1, Q2, Q3 and Q4). The instruction fetch and execute are pipelined such that fetch takes one instruction cycle while decode and execute takes another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the program counter to change, (e.g.
PIC16F62X NOTES: DS40300C-page 12 Preliminary 2003 Microchip Technology Inc.
PIC16F62X 3.0 MEMORY ORGANIZATION 3.2 3.1 Program Memory Organization The data memory (Figure 3-2) is partitioned into four banks, which contain the general purpose registers and the Special Function Registers (SFR). The SFR’s are located in the first 32 locations of each Bank. Register locations 20-7Fh, A0h-FFh, 120h-14Fh, 170h-17Fh and 1F0h-1FFh are general purpose registers implemented as static RAM. The PIC16F62X has a 13-bit program counter capable of addressing an 8K x 14 program memory space.
PIC16F62X FIGURE 3-2: DATA MEMORY MAP OF THE PIC16F627 AND PIC16F628 File Address Indirect addr.(1) 00h Indirect addr.(1) 80h Indirect addr.(1) 100h Indirect addr.
PIC16F62X 3.2.2 SPECIAL FUNCTION REGISTERS The SFRs are registers used by the CPU and Peripheral functions for controlling the desired operation of the device (Table 3-1). These registers are static RAM. The special registers can be classified into two sets (core and peripheral). The SFRs associated with the “core” functions are described in this section. Those related to the operation of the peripheral features are described in the section of that peripheral feature.
PIC16F62X TABLE 3-2: Address SPECIAL FUNCTION REGISTERS SUMMARY BANK 1 Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR Reset(1) Details on Page xxxx xxxx 25 1111 1111 20 Bank 1 80h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 81h OPTION 82h PCL RBPU 83h STATUS 84h 85h FSR TRISA Indirect data memory address pointer TRISA7 TRISA6 TRISA5 TRISA4 86h 87h TRISB — TRISB7 TRISB6 Unimplemented 88h — INTEDG T0C
PIC16F62X TABLE 3-3: Address SPECIAL FUNCTION REGISTERS SUMMARY BANK 2 Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR Reset(1) Details on Page xxxx xxxx 25 1111 1111 43 Bank 2 100h INDF 101h TMR0 102h PCL 103h STATUS 104h 105h FSR 106h 107h PORTB — 108h — Addressing this location uses contents of FSR to address data memory (not a physical register) RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 Program Counter's (PC) Least Significant Byte — IRP RP1 RP0 T
PIC16F62X TABLE 3-4: Address SPECIAL FUNCTION REGISTERS SUMMARY BANK 3 Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR Reset(1) Details on Page Bank 3 180h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 25 1111 1111 20 181h OPTION RBPU 182h PCL Program Counter's (PC) Least Significant Byte 183h STATUS IRP 184h 185h FSR Indirect data memory address pointer Unimplemented 186h 187h TRISB — 188h —
PIC16F62X 3.2.2.1 STATUS Register The STATUS register, shown in Register 3-1, contains the arithmetic status of the ALU, the RESET status and the bank select bits for data memory (SRAM). The STATUS register can be the destination for any instruction, like any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic.
PIC16F62X 3.2.2.2 OPTION Register Note: The OPTION register is a readable and writable register which contains various control bits to configure the TMR0/WDT prescaler, the external RB0/INT interrupt, TMR0, and the weak pull-ups on PORTB. REGISTER 3-2: To achieve a 1:1 prescaler assignment for TMR0, assign the prescaler to the WDT (PSA = 1). See Section 6.3.
PIC16F62X 3.2.2.3 INTCON Register Note: The INTCON register is a readable and writable register which contains the various enable and flag bits for all interrupt sources except the comparator module. See Section 3.2.2.4 and Section 3.2.2.5 for a description of the comparator enable and flag bits. REGISTER 3-3: Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>).
PIC16F62X 3.2.2.4 PIE1 Register This register contains interrupt enable bits.
PIC16F62X 3.2.2.5 PIR1 Register Note: This register contains interrupt flag bits. REGISTER 3-5: Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
PIC16F62X 3.2.2.6 PCON Register The PCON register contains flag bits to differentiate between a Power-on Reset, an external MCLR Reset, WDT Reset or a Brown-out Detect. REGISTER 3-6: Note: BOD is unknown on Power-on Reset. It must then be set by the user and checked on subsequent RESETS to see if BOD is cleared, indicating a brown-out has occurred.
PIC16F62X 3.3 PCL and PCLATH The program counter (PC) is 13-bits wide. The low byte comes from the PCL register, which is a readable and writable register. The high byte (PC<12:8>) is not directly readable or writable and comes from PCLATH. On any RESET, the PC is cleared. Figure 3-3 shows the two situations for the loading of the PC. The upper example in the figure shows how the PC is loaded on a write to PCL (PCLATH<4:0> → PCH).
PIC16F62X FIGURE 3-4: DIRECT/INDIRECT ADDRESSING PIC16F62X Direct Addressing RP1 RP0 bank select 6 from opcode Indirect Addressing 0 IRP 7 bank select location select 00 01 10 FSR register 0 location select 11 00h 180h RAM File Registers 7Fh 1FFh Bank 0 Note: Bank 1 Bank 2 Bank 3 For memory map detail see Figure 3-2. DS40300C-page 26 Preliminary 2003 Microchip Technology Inc.
PIC16F62X 4.0 GENERAL DESCRIPTION The PIC16F62X are 18-Pin FLASH-based members of the versatile PIC16CXX family of low cost, high performance, CMOS, fully static, 8-bit microcontrollers. All PICmicro® microcontrollers employ an advanced RISC architecture. The PIC16F62X have enhanced core features, eight-level deep stack, and multiple internal and external interrupt sources.
PIC16F62X NOTES: DS40300C-page 28 Preliminary 2003 Microchip Technology Inc.
PIC16F62X 5.0 I/O PORTS The PIC16F62X have two ports, PORTA and PORTB. Some pins for these I/O ports are multiplexed with an alternate function for the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. 5.1 2: TRISA<6:7> is overridden by oscillator configuration. When PORTA<6:7> is overridden, the data reads ‘0’ and the TRISA<6:7> bits are ignored. PORTA and TRISA Registers PORTA is an 8-bit wide latch.
PIC16F62X FIGURE 5-1: Data Bus BLOCK DIAGRAM OF RA0/AN0:RA1/AN1 PINS D WR PORTA Data Bus Q CK FIGURE 5-2: D VDD WR PORTA Q BLOCK DIAGRAM OF RA2/VREF PIN Q CK Q Data Latch Data Latch D D WR TRISA Q CK VDD Q I/O Pin RA2 Pin WR TRISA Q TRIS Latch CK Q VSS TRIS Latch VSS Analog Input Mode Analog Input Mode RD TRISA Schmitt Trigger Input Buffer Schmitt Trigger Input Buffer RD TRISA Q Q D D EN EN RD PORTA RD PORTA To Comparator To Comparator VROE VREF FIGURE 5-3: Data Bus
PIC16F62X FIGURE 5-4: Data Bus BLOCK DIAGRAM OF RA4/T0CKI PIN Comparator Mode = 110 D Q Comparator Output WR PORTA VDD 1 CK Q 0 Data Latch D Q RA4 Pin N WR TRISA CK Q Vss TRIS Latch Vss Schmitt Trigger Input Buffer RD TRISA Q D EN RD PORTA TMR0 Clock Input FIGURE 5-5: BLOCK DIAGRAM OF THE FIGURE 5-6: BLOCK DIAGRAM OF RA6/OSC2/CLKOUT PIN RA5/MCLR/VPP PIN From OSC1 OSC Circuit VDD CLKOUT(FOSC/4) 1 MCLRE MCLR circuit MCLR Filter Q 0 CK Q (FOSC = Data Latch (2) 101, 111) Schmitt
PIC16F62X FIGURE 5-7: BLOCK DIAGRAM OF RA7/OSC1/CLKIN PIN To OSC2 Oscillator Circuit VDD CLKIN to core Data Bus D WR PORTA Q RA7/OSC1/CLKIN Pin CK Q Data Latch D WR TRISA CK VSS Q Q TRIS Latch RD TRISA FOSC = 100, 101(1) Q D Schmitt Trigger Input Buffer EN RD PORTA Note 1: DS40300C-page 32 INTRC with CLKOUT, and INTRC with I/O. Preliminary 2003 Microchip Technology Inc.
PIC16F62X TABLE 5-1: PORTA FUNCTIONS Name RA0/AN0 RA1/AN1 RA2/AN2/VREF RA3/AN3/CMP1 RA4/T0CKI/CMP2 RA5/MCLR/VPP Functio n Input Type Output Type RA0 AN0 RA1 AN1 RA2 AN2 VREF RA3 AN3 CMP1 RA4 T0CKI ST AN ST AN ST AN — ST AN — ST ST CMOS — CMOS — CMOS — AN CMOS — CMOS OD — CMP2 — OD RA5 ST — Bi-directional I/O port Analog comparator input Bi-directional I/O port Analog comparator input Bi-directional I/O port Analog comparator input VREF output Bi-directional I/O port Analog comparator input
PIC16F62X TABLE 5-2: Address SUMMARY OF REGISTERS ASSOCIATED WITH PORTA(1) Name Bit 7 Bit 6 Bit 5 Bit 4 RA5 RA4 05h PORTA RA7 RA6 85h TRISA TRISA7 TRISA6 TRISA5 TRISA4 1Fh CMCON C2OUT C1OUT C2INV 9Fh VRCON VREN VROE VRR Bit 3 Bit 2 Bit 1 Bit 0 Value on POR Value on All Other RESETS xxxu 0000 RA3 RA2 RA1 RA0 xxxx 0000 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 1111 1111 C1INV CIS CM2 CM1 CM0 0000 0000 0000 0000 — VR3 VR2 VR1 VR0 000- 0000 000- 0000 Legend
PIC16F62X FIGURE 5-8: BLOCK DIAGRAM OF RB0/INT PIN FIGURE 5-9: BLOCK DIAGRAM OF RB1/RX/DT PIN VDD VDD RBPU RBPU P Weak Pull-up PORT/PERIPHERAL Weak P Pull-up VDD Select(1) VDD USART Data Output Data Bus WR PORTB D WR TRISB CK D Q WR PORTB CK Q Q Data Latch D Data Bus Q RB0/INT CK 0 WR TRISB Q Peripheral OE(2) TRIS Latch RB1/ RX/DT VSS Data Latch VSS Q 1 D Q CK Q TRIS Latch TTL Input Buffer RD TRISB TTL Input Buffer RD TRISB Q Q D EN D RD PORTB EN EN USART Rece
PIC16F62X FIGURE 5-10: BLOCK DIAGRAM OF RB2/TX/CK PIN VDD Weak P Pull-up VDD RBPU PORT/PERIPHERAL Select(1) USART TX/CK Output D Q WR PORTB CK Q RB2/ TX/CK 1 Q CK Q WR TRISB PORT/PERIPHERAL Select(1) 0 Data Bus D Q WR PORTB CK Q TRIS Latch Peripheral OE(2) TTL Input Buffer RD TRISB D Q CK Q VSS TRIS Latch TTL Input Buffer RD TRISB D Q EN RD PORTB EN USART Slave Clock In Schmitt Trigger 1: 2: D RD PORTB USART Slave Clock In Note RB3/ CCP1 1 Data Latch WR TRISB
PIC16F62X FIGURE 5-12: BLOCK DIAGRAM OF RB4/PGM PIN VDD RBPU P weak pull-up Data Bus WR PORTB D Q CK Q VDD Data Latch WR TRISB D Q CK Q RB4/PGM VSS TRIS Latch RD TRISB LVP RD PORTB PGM input TTL input buffer Schmitt Trigger Q D EN Q1 Set RBIF Q From other RB<7:4> pins D Q3 EN Note 1: The low voltage programming disables the interrupt-on-change and the weak pull-ups on RB4. 2003 Microchip Technology Inc.
PIC16F62X FIGURE 5-13: BLOCK DIAGRAM OF RB5 PIN VDD RBPU weak VDD P pull-up Data Bus D Q CK Q RB5 pin WR PORTB Data Latch VSS D Q CK Q WR TRISB TRIS Latch TTL input buffer RD TRISB Q D RD PORTB EN Q1 Set RBIF Q From other RB<7:4> pins D Q3 EN DS40300C-page 38 Preliminary 2003 Microchip Technology Inc.
PIC16F62X FIGURE 5-14: BLOCK DIAGRAM OF RB6/T1OSO/T1CKI PIN VDD RBPU P weak pull-up Data Bus WR PORTB D Q CK Q VDD Data Latch WR TRISB D Q CK Q RB6/ T1OSO/ T1CKI pin VSS TRIS Latch RD TRISB T1OSCEN TTL input buffer RD PORTB TMR1 Clock From RB7 Schmitt Trigger TMR1 oscillator Serial programming clock Q D EN Set RBIF From other RB<7:4> pins Q D Q3 EN 2003 Microchip Technology Inc.
PIC16F62X FIGURE 5-15: BLOCK DIAGRAM OF THE RB7/T1OSI PIN VDD RBPU P weak pull-up TMR1 oscillator To RB6 VDD Data Bus WR PORTB D Q CK Q RB7/T1OSI pin Data Latch WR TRISB D Q CK Q VSS TRIS Latch RD TRISB T10SCEN TTL input buffer RD PORTB Serial programming input Schmitt Trigger Q D EN Set RBIF From other RB<7:4> pins Q D EN DS40300C-page 40 Preliminary 2003 Microchip Technology Inc.
PIC16F62X TABLE 5-3: PORTB FUNCTIONS Name Function Input Type Output Type RB0/INT RB0 TTL CMOS RB1/RX/DT INT RB1 ST TTL — CMOS RB2/TX/CK RX DT RB2 TX CK RB3/CCP1 RB3 RB4/PGM CCP1 RB4 RB5 RB6/T1OSO/T1CKI/ PGC RB6 T1OSO T1CKI PGC RB7 RB7/T1OSI/PGD T1OSI PGD Legend: O = Output — = Not used TTL = TTL Input TABLE 5-4: Address Bi-directional I/O port. Can be software programmed for internal weak pull-up. External interrupt. Bi-directional I/O port.
PIC16F62X 5.3 I/O Programming Considerations 5.3.1 EXAMPLE 5-2: BI-DIRECTIONAL I/O PORTS Any instruction which writes, operates internally as a read followed by a write operation. The BCF and BSF instructions, for example, read the register into the CPU, execute the bit operation and write the result back to the register. Caution must be used when these instructions are applied to a port with both inputs and outputs defined.
PIC16F62X 6.0 TIMER0 MODULE 6.2 The Timer0 module timer/counter has the following features: • • • • • • 8-bit timer/counter Readable and writable 8-bit software programmable prescaler Internal or external clock select Interrupt on overflow from FFh to 00h Edge select for external clock Timer mode is selected by clearing the T0CS bit (OPTION<5>). In Timer mode, the TMR0 will increment every instruction cycle (without prescaler).
PIC16F62X 6.3 Timer0 Prescaler The PSA and PS2:PS0 bits (OPTION<3:0>) determine the prescaler assignment and prescale ratio. An 8-bit counter is available as a prescaler for the Timer0 module, or as a postscaler for the Watchdog Timer. A prescaler assignment for the Timer0 module means that there is no postscaler for the Watchdog Timer, and vice-versa. FIGURE 6-1: When assigned to the Timer0 module, all instructions writing to the TMR0 register (e.g., CLRF 1, MOVWF 1, BSF 1, x....etc.
PIC16F62X 6.3.1 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software control (i.e., it can be changed “on the fly” during program execution). Use the instruction sequences, shown in Example 6-1, when changing the prescaler assignment from Timer0 to WDT, to avoid an unintended device RESET.
PIC16F62X 7.0 TIMER1 MODULE The Operating mode is determined by the clock select bit, TMR1CS (T1CON<1>). The Timer1 module is a 16-bit timer/counter consisting of two 8-bit registers (TMR1H and TMR1L) which are readable and writable. The TMR1 Register pair (TMR1H:TMR1L) increments from 0000h to FFFFh and rolls over to 0000h. The TMR1 Interrupt, if enabled, is generated on overflow which is latched in interrupt flag bit TMR1IF (PIR1<0>).
PIC16F62X 7.1 Timer1 Operation in Timer Mode 7.2.1 Timer mode is selected by clearing the TMR1CS (T1CON<1>) bit. In this mode, the input clock to the timer is FOSC/4. The synchronize control bit T1SYNC (T1CON<2>) has no effect since the internal clock is always in sync. 7.2 Timer1 Operation in Synchronized Counter Mode Counter mode is selected by setting bit TMR1CS.
PIC16F62X 7.3 Timer1 Operation in Asynchronous Counter Mode EXAMPLE 7-1: If control bit T1SYNC (T1CON<2>) is set, the external clock input is not synchronized. The timer continues to increment asynchronous to the internal phase clocks. The timer will continue to run during SLEEP and can generate an interrupt on overflow which will wake-up the processor. However, special precautions in software are needed to read/write the timer (Section 7.3.2).
PIC16F62X 7.4 Timer1 Oscillator 7.5 A crystal oscillator circuit is built in between pins T1OSI (input) and T1OSO (amplifier output). It is enabled by setting control bit T1OSCEN (T1CON<3>). The oscillator is a low power oscillator rated up to 200 kHz. It will continue to run during SLEEP. It is primarily intended for a 32 kHz crystal. Table 7-1 shows the capacitor selection for the Timer1 oscillator.
PIC16F62X 8.0 TIMER2 MODULE 8.1 Timer2 is an 8-bit timer with a prescaler and a postscaler. It can be used as the PWM time-base for PWM mode of the CCP module. The TMR2 register is readable and writable, and is cleared on any device RESET. The input clock (FOSC/4) has a prescale option of 1:1, 1:4 or 1:16, selected by control bits T2CKPS1:T2CKPS0 (T2CON<1:0>). The Timer2 module has an 8-bit Period Register PR2.
PIC16F62X REGISTER 8-1: T2CON: TIMER CONTROL REGISTER (ADDRESS: 12h) U-0 R/W-0 — R/W-0 R/W-0 TOUTPS3 TOUTPS2 TOUTPS1 R/W-0 R/W-0 TOUTPS0 R/W-0 R/W-0 TMR2ON T2CKPS1 T2CKPS0 bit 7 bit 0 bit 7 Unimplemented: Read as '0' bit 6-3 TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits 0000 = 1:1 Postscale Value 0001 = 1:2 Postscale Value • • • 1111 = 1:16 Postscale bit 2 TMR2ON: Timer2 On bit 1 = Timer2 is on 0 = Timer2 is off bit 1-0 T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits 00 = 1:1
PIC16F62X NOTES: DS40300C-page 52 Preliminary 2003 Microchip Technology Inc.
PIC16F62X 9.0 COMPARATOR MODULE The Comparator module contains two analog comparators. The inputs to the comparators are multiplexed with the RA0 through RA3 pins. The Onchip Voltage Reference (Section 10.0) can also be an input to the comparators. REGISTER 9-1: The CMCON register, shown in Register 9-1, controls the comparator input and output multiplexers. A block diagram of the comparator is shown in Figure 9-1.
PIC16F62X 9.1 Comparator Configuration There are eight modes of operation for the comparators. The CMCON register is used to select the mode. Figure 9-1 shows the eight possible modes. The TRISA register controls the data direction of the comparator pins for each mode. If the Comparator FIGURE 9-1: mode is changed, the comparator output level may not be valid for the specified mode change delay shown in Table 17-1.
PIC16F62X The code example in Example 9-1 depicts the steps required to configure the Comparator module. RA3 and RA4 are configured as digital output. RA0 and RA1 are configured as the V- inputs and RA2 as the V+ input to both comparators.
PIC16F62X 9.5 Comparator Outputs The comparator outputs are read through the CMCON register. These bits are read only. The comparator outputs may also be directly output to the RA3 and RA4 I/O pins. When the CM<2:0> = 110, multiplexors in the output path of the RA3 and RA4/T0CK1 pins will switch and the output of each pin will be the unsynchronized output of the comparator. The uncertainty of each of the comparators is related to the input offset voltage and the response time given in the specifications.
PIC16F62X 9.6 Comparator Interrupts 9.7 The Comparator Interrupt flag is set whenever there is a change in the output value of either comparator. Software will need to maintain information about the status of the output bits, as read from CMCON<7:6>, to determine the actual change that has occurred. The CMIF bit, PIR1<6>, is the Comparator Interrupt Flag. The CMIF bit must be RESET by clearing ‘0’. Since it is also possible to write a '1' to this register, a simulated interrupt may be initiated.
PIC16F62X FIGURE 9-4: ANALOG INPUT MODE VDD VT = 0.6V RS < 10K AIN CPIN 5 pF VA VT = 0.
PIC16F62X 10.0 VOLTAGE REFERENCE MODULE 10.1 The Voltage Reference can output 16 distinct voltage levels for each range. The Voltage Reference is a 16-tap resistor ladder network that provides a selectable voltage reference. The resistor ladder is segmented to provide two ranges of VREF values and has a power-down function to conserve power when the reference is not being used. The VRCON register controls the operation of the reference as shown in Figure 10-1. The block diagram is given in Figure 10-1.
PIC16F62X EXAMPLE 10-1: 10.4 VOLTAGE REFERENCE CONFIGURATION MOVLW 0x02 ; 4 Inputs Muxed MOVWF BSF CMCON STATUS,RP0 ; to 2 comps. ; go to Bank 1 MOVLW MOVWF 0x07 TRISA ; RA3-RA0 are ; outputs MOVLW 0xA6 ; enable VREF MOVWF VRCON ; low range A device RESET disables the Voltage Reference by clearing bit VREN (VRCON<7>). This RESET also disconnects the reference from the RA2 pin by clearing bit VROE (VRCON<6>) and selects the high voltage range by clearing bit VRR (VRCON<5>).
PIC16F62X 11.0 CAPTURE/COMPARE/PWM (CCP) MODULE TABLE 11-1: The CCP (Capture/Compare/PWM) module contains a 16-bit register which can operate as a 16-bit capture register, as a 16-bit compare register or as a PWM master/slave Duty Cycle register. Table 11-1 shows the timer resources of the CCP Module modes.
PIC16F62X 11.1 Capture Mode In Capture mode, CCPR1H:CCPR1L captures the 16-bit value of the TMR1 register when an event occurs on pin RB3/CCP1. An event is defined as: • • • • Every falling edge Every rising edge Every 4th rising edge Every 16th rising edge EXAMPLE 11-1: An event is selected by control bits CCP1M3:CCP1M0 (CCP1CON<3:0>). When a capture is made, the Interrupt Request Flag bit CCP1IF (PIR1<2>) is set. It must be cleared in software.
PIC16F62X 11.2.2 TIMER1 MODE SELECTION 11.2.4 Timer1 must be running in Timer mode or Synchronized Counter mode if the CCP module is using the compare feature. In Asynchronous Counter mode, the compare operation may not work. 11.2.3 SPECIAL EVENT TRIGGER In this mode, an internal hardware trigger is generated which may be used to initiate an action. The special event trigger output of CCP1 resets the TMR1 register pair.
PIC16F62X 11.3 PWM Mode In Pulse Width Modulation (PWM) mode, the CCP1 pin produces up to a 10-bit resolution PWM output. Since the CCP1 pin is multiplexed with the PORTB data latch, the TRISB<3> bit must be cleared to make the CCP1 pin an output. Note: A PWM output (Figure 11-3) has a time-base (period) and a time that the output stays high (duty cycle). The frequency of the PWM is the inverse of the period (1/period).
PIC16F62X 11.3.2 PWM DUTY CYCLE EQUATION 11-2: The PWM duty cycle is specified by writing to the CCPR1L register and to the CCP1CON<5:4> bits. Up to 10-bit resolution is available: the CCPR1L contains the eight MSbs and the CCP1CON<5:4> contains the two LSbs. This 10-bit value is represented by CCPR1L:CCP1CON<5:4>. The following equation is used to calculate the PWM duty cycle in time: EQUATION 11-1: Note: The CCPR1H register and a 2-bit internal latch are used to double buffer the PWM duty cycle.
PIC16F62X NOTES: DS40300C-page 66 Preliminary 2003 Microchip Technology Inc.
PIC16F62X 12.0 UNIVERSAL SYNCHRONOUS/ ASYNCHRONOUS RECEIVER/ TRANSMITTER (USART) MODULE The USART can be configured in the following modes: • Asynchronous (full duplex) • Synchronous - Master (half duplex) • Synchronous - Slave (half duplex) Bit SPEN (RCSTA<7>), and bits TRISB<2:1>, have to be set in order to configure pins RB2/TX/CK and RB1/ RX/DT as the Universal Synchronous Asynchronous Receiver Transmitter.
PIC16F62X REGISTER 12-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER (ADDRESS: 18h) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x SPEN RX9 SREN CREN ADEN FERR OERR RX9D bit 7 bit 0 bit 7 SPEN: Serial Port Enable bit (Configures RB1/RX/DT and RB2/TX/CK pins as serial port pins when bits TRISB<2:17> are set) 1 = Serial port enabled 0 = Serial port disabled bit 6 RX9: 9-bit Receive Enable bit 1 = Selects 9-bit reception 0 = Selects 8-bit reception bit 5 SREN: Single Receive Enable bit Asynch
PIC16F62X 12.1 USART Baud Rate Generator (BRG) EXAMPLE 12-1: The BRG supports both the Asynchronous and Synchronous modes of the USART. It is a dedicated 8-bit baud rate generator. The SPBRG register controls the period of a free running 8-bit timer. In Asynchronous mode bit BRGH (TXSTA<2>) also controls the baud rate. In Synchronous mode bit BRGH is ignored. Table 12-1 shows the formula for computation of the baud rate for different USART modes which only apply in Master mode (internal clock).
PIC16F62X TABLE 12-3: BAUD RATE (K) 0.3 1.2 2.4 9.6 19.2 76.8 96 300 500 HIGH LOW BAUD RATE (K) BAUD RATES FOR SYNCHRONOUS MODE FOSC = 20 MHz KBAUD ERROR NA NA NA NA 19.53 76.92 96.15 294.1 500 5000 19.53 — — — — +1.73% +0.16% +0.16% -1.96 0 — — FOSC = 7.15909 MHz SPBRG 16 MHz value KBAUD (decimal) — — — — 255 64 51 16 9 0 255 NA NA NA NA 19.23 76.92 95.24 307.69 500 4000 15.625 SPBRG 5.0688 MHz value KBAUD (decimal) ERROR — — — — +0.16% +0.16% -0.79% +2.
PIC16F62X TABLE 12-4: BAUD RATE (K) 0.3 1.2 2.4 9.6 19.2 76.8 96 300 500 HIGH LOW BAUD RATE (K) 0.3 1.2 2.4 9.6 19.2 76.8 96 300 500 HIGH LOW BAUD RATE (K) 0.3 1.2 2.4 9.6 19.2 76.8 96 300 500 HIGH LOW BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 0) FOSC = 20 MHz KBAUD ERROR NA 1.221 2.404 9.469 19.53 78.13 104.2 312.5 NA 312.5 1.221 — +1.73% +0.16% -1.36% +1.73% +1.73% +8.51% +4.17% — — — FOSC = 7.15909 MHz KBAUD ERROR NA 1.203 2.380 9.322 18.64 NA NA NA NA 111.9 0.437 — +0.23% -0.83% -2.90% -2.
PIC16F62X TABLE 12-5: BAUD RATE (K) 9600 19200 38400 57600 115200 250000 625000 1250000 BAUD RATE (K) 9600 19200 38400 57600 115200 250000 625000 1250000 BAUD RATE (K) 9600 19200 38400 57600 115200 250000 625000 1250000 BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 1) FOSC = 20 MHz KBAUD ERROR 9.615 19.230 37.878 56.818 113.636 250 625 1250 +0.16% +0.16% -1.36% -1.36% -1.36% 0 0 0 FOSC = 7.16 MHz KBAUD ERROR 9.520 19.454 37.286 55.930 111.860 NA NA NA -0.83% +1.32% -2.90% -2.90% -2.
PIC16F62X The data on the RB1/RX/DT pin is sampled three times by a majority detect circuit to determine if a high or a low level is present at the RX pin. If bit BRGH (TXSTA<2>) is clear (i.e., at the low baud rates), the sampling is done on the seventh, eighth and ninth falling edges of a x16 clock (Figure 12-3). If bit BRGH is set (i.e.
PIC16F62X FIGURE 12-4: RX PIN SAMPLING SCHEME, BRGH = 0 OR BRGH = 1 START bit RX (RB1/RX/DT pin) Bit0 Baud CLK for all but START bit Baud CLK x16 CLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 Samples 12.2 USART Asynchronous Mode In this mode, the USART uses standard non-return to zero (NRZ) format (one START bit, eight or nine data bits and one STOP bit). The most common data format is 8 bits.
PIC16F62X FIGURE 12-5: USART TRANSMIT BLOCK DIAGRAM Data Bus TXIF TXREG register 8 TXIE MSb (8) LSb 0 2 2 2 Pin Buffer and Control TSR register RB2/TX/CK pin Interrupt TXEN Baud Rate CLK TRMT SPEN SPBRG TX9 Baud Rate Generator TX9D Steps to follow when setting up an Asynchronous Transmission: 1. 2. 3. 4. 5. 6. 7. Initialize the SPBRG register for the appropriate baud rate. If a high speed baud rate is desired, set bit BRGH. (Section 12.
PIC16F62X FIGURE 12-7: ASYNCHRONOUS TRANSMISSION (BACK TO BACK) Write to TXREG WORD 1 BRG output (shift clock) RB2/TX/CK (pin) START Bit TXIF bit (interrupt reg. flag) TRMT bit (Transmit shift reg. empty flag) Note 1: Bit 1 WORD 1 Bit 7/8 STOP Bit START Bit Bit 0 WORD 2 WORD 2 Transmit Shift Reg. This.timing diagram shows two consecutive transmissions.
PIC16F62X 12.2.2 ADEN USART ASYNCHRONOUS RECEIVER It is possible for two bytes of data to be received and transferred to the RCREG FIFO, and a third byte begin shifting to the RSR register. On the detection of the STOP bit of the third byte, if the RCREG register is still full, then overrun error bit OERR (RCSTA<1>) will be set. The word in the RSR will be lost. The RCREG register can be read twice to retrieve the two bytes in the FIFO. Overrun bit OERR has to be cleared in software.
PIC16F62X FIGURE 12-9: RB1/RX/DT (PIN) ASYNCHRONOUS RECEPTION WITH ADDRESS DETECT START BIT BIT0 BIT1 BIT8 STOP BIT START BIT BIT0 BIT8 STOP BIT RCV SHIFT REG RCV BUFFER REG BIT8 = 0, DATA BYTE BIT8 = 1, ADDRESS BYTE READ RCV BUFFER REG RCREG WORD 1 RCREG RCIF (INTERRUPT FLAG) '1' ADEN = 1 (ADDRESS MATCH ENABLE) '1' Note 1: This timing diagram shows a data byte followed by an address byte. The data byte is not read into the RCREG (Receive Buffer) because ADEN = 1 and Bit 8 = 0.
PIC16F62X Steps to follow when setting up an Asynchronous Reception: 1. 2. 3. 4. 5. 6. 7. 8. 9. Initialize the SPBRG register for the appropriate baud rate. If a high speed baud rate is desired, set bit BRGH. (Section 12.1). Enable the asynchronous serial port by clearing bit SYNC, and setting bit SPEN. If interrupts are desired, then set enable bit RCIE. If 9-bit reception is desired, then set bit RX9. Enable the reception by setting bit CREN.
PIC16F62X 12.3 USART Function The USART function is similar to that on the PIC16C74B, which includes the BRGH = 1 fix. 12.3.1 The USART Receive Block Diagram is shown in Figure 12-8. USART 9-BIT RECEIVER WITH ADDRESS DETECT When the RX9 bit is set in the RCSTA register, 9 bits are received and the ninth bit is placed in the RX9D bit of the RCSTA register. The USART module has a special provision for multiprocessor communication.
PIC16F62X 12.4 USART Synchronous Master Mode In Synchronous Master mode, the data is transmitted in a half-duplex manner (i.e., transmission and reception do not occur at the same time). When transmitting data, the reception is inhibited and vice versa. Synchronous mode is entered by setting bit SYNC (TXSTA<4>). In addition, enable bit SPEN (RCSTA<7>) is set in order to configure the RB2/TX/CK and RB1/RX/DT I/O pins to CK (clock) and DT (data) lines respectively.
PIC16F62X TABLE 12-9: Address REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR Value on all other RESETS EEIF CMIF RCIF TXIF — CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000 0Ch PIR1 18h RCSTA SPEN RX9 SREN CREN ADEN FERR OERR RX9D 0000 -00x 0000 -00x 19h TXREG USART Transmit Register 0000 0000 0000 0000 EEIE CMIE RCIE TXIE — CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000 8Ch PIE1 98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -
PIC16F62X 12.4.2 USART SYNCHRONOUS MASTER RECEPTION receive bit is buffered the same way as the receive data. Reading the RCREG register, will load bit RX9D with a new value, therefore it is essential for the user to read the RCSTA register before reading RCREG in order not to lose the old RX9D information. Once Synchronous mode is selected, reception is enabled by setting either enable bit SREN (RCSTA<5>) or enable bit CREN (RCSTA<4>).
PIC16F62X FIGURE 12-14: SYNCHRONOUS RECEPTION (MASTER MODE, SREN) Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 RB1/RX/DT PIN BIT0 BIT1 BIT2 BIT3 BIT4 BIT5 BIT6 BIT7 RB2/TX/CK PIN WRITE TO BIT SREN SREN BIT CREN BIT '0' '0' RCIF BIT (INTERRUPT) READ RXREG Note 1: Timing diagram demonstrates Sync Master mode with bit SREN = ‘1’ and bit BRG = ‘0’. 12.
PIC16F62X 12.5.2 USART SYNCHRONOUS SLAVE RECEPTION 2. The operation of the Synchronous Master and Slave modes is identical except in the case of the SLEEP mode. Also, bit SREN is a don't care in Slave mode. 3. 4. 5. If receive is enabled, by setting bit CREN, prior to the SLEEP instruction, then a word may be received during SLEEP.
PIC16F62X NOTES: DS40300C-page 86 Preliminary 2003 Microchip Technology Inc.
PIC16F62X 13.0 DATA EEPROM MEMORY The EEPROM data memory is readable and writable during normal operation (full VDD range). This memory is not directly mapped in the register file space. Instead it is indirectly addressed through the Special Function Registers (SFRs). There are four SFRs used to read and write this memory. These registers are: The EEPROM data memory allows byte read and write. A byte write automatically erases the location and writes the new data (erase before write).
PIC16F62X REGISTER 13-2: EECON1 REGISTER (ADDRESS: 9Ch) U-0 U-0 U-0 U-0 R/W-x R/W-0 R/S-0 R/S-x — — — — WRERR WREN WR RD bit 7 bit 0 bit 7-4 Unimplemented: Read as '0' bit 3 WRERR: EEPROM Error Flag bit 1 = A write operation is prematurely terminated (any MCLR Reset, any WDT Reset during normal operation or BOD Reset) 0 = The write operation completed bit 2 WREN: EEPROM Write Enable bit 1 = Allows write cycles 0 = Inhibits write to the data EEPROM bit 1 WR: Write Control bit 1 = In
PIC16F62X 13.3 READING THE EEPROM DATA MEMORY To read a data memory location, the user must write the address to the EEADR register and then set control bit RD (EECON1<0>). The data is available, in the very next cycle, in the EEDATA register; therefore it can be read in the next instruction. EEDATA will hold this value until another read or until it is written to by the user (during a write operation). EXAMPLE 13-1: BSF MOVLW MOVWF BSF MOVF BCF 13.
PIC16F62X TABLE 13-1: Address REGISTERS/BITS ASSOCIATED WITH DATA EEPROM Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 9Ah 9Bh 9Ch 9Dh Legend: Note Bit 1 Bit 0 EEDATA EEPROM data register EEADR EEPROM address register EECON1 — — — — WRERR WREN WR RD EECON2(1) EEPROM control register 2 x = unknown, u = unchanged, - = unimplemented read as '0', q = value depends upon condition. Shaded cells are not used by data EEPROM.
PIC16F62X 14.0 SPECIAL FEATURES OF THE CPU Special circuits to deal with the needs of real-time applications are what sets a microcontroller apart from other processors. The PIC16F62X family has a host of such features intended to maximize system reliability, minimize cost through elimination of external components, provide power saving Operating modes and offer code protection. These are: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 14.
PIC16F62X REGISTER 14-1: CONFIGURATION WORD CP1 CP0 CP1 CP0 — CPD LVP BODEN MCLRE FOSC2 PWRTE WDTE F0SC1 bit 13 bit 13-10: F0SC0 bit 0 CP1:CP0: Code Protection bits (2) Code protection for 2K program memory 11 = Program memory code protection off 10 = 0400h-07FFh code protected 01 = 0200h-07FFh code protected 00 = 0000h-07FFhcode protected Code protection for 1K program memory 11 = Program memory code protection off 10 = Program memory code protection off 01 = 0200h-03FFh code protected 00 =
PIC16F62X 14.2 Oscillator Configurations 14.2.1 TABLE 14-1: OSCILLATOR TYPES Ranges Characterized: The PIC16F62X can be operated in eight different oscillator options. The user can program three configuration bits (FOSC2 thru FOSC0) to select one of these eight modes: • • • • • • LP XT HS ER INTRC EC 14.2.
PIC16F62X FIGURE 14-2: 14.2.5 EXTERNAL PARALLEL RESONANT CRYSTAL OSCILLATOR CIRCUIT For timing insensitive applications, the ER (External Resistor) Clock mode offers additional cost savings. Only one external component, a resistor to VSS, is needed to set the operating frequency of the internal oscillator. The resistor draws a DC bias current which controls the oscillation frequency.
PIC16F62X 14.2.6 INTERNAL 4 MHZ OSCILLATOR 14.4 The internal RC oscillator provides a fixed 4 MHz (nominal) system clock at VDD = 5V and 25°C, see “Electrical Specifications” section for information on variation over voltage and temperature. 14.2.7 CLKOUT The PIC16F62X can be configured to provide a clock out signal by programming the configuration word. The oscillator frequency, divided by 4 can be used for test purposes or to synchronize other logic. 14.
PIC16F62X 14.5 14.5.1 Power-on Reset (POR), Power-up Timer (PWRT), Oscillator Start-up Timer (OST) and Brown-out Detect (BOD) The Power-Up Time delay will vary from chip to chip and due to VDD, temperature and process variation. See DC parameters for details. 14.5.3 POWER-ON RESET (POR) The OST provides a 1024 oscillator cycle (from OSC1 input) delay after the PWRT delay is over. This ensures that the crystal oscillator or resonator has started and stabilized.
PIC16F62X 14.5.5 TIMEOUT SEQUENCE 14.5.6 On power-up the timeout sequence is as follows: First PWRT timeout is invoked after POR has expired. Then OST is activated. The total timeout will vary based on oscillator configuration and PWRTE bit status. For example, in ER mode with PWRTE bit erased (PWRT disabled), there will be no timeout at all. Figure 14-8, Figure 14-9 and Figure 14-10 depict timeout sequences. The Power Control/STATUS register, PCON (address 8Eh) has two bits. Bit0 is BOD (Brown-out).
PIC16F62X TABLE 14-7: INITIALIZATION CONDITION FOR SPECIAL REGISTERS Program Counter STATUS Register PCON Register Power-on Reset 000h 0001 1xxx ---- 1-0x MCLR Reset during normal operation 000h 000u uuuu ---- 1-uu MCLR Reset during SLEEP 000h 0001 0uuu ---- 1-uu WDT Reset 000h 0000 uuuu ---- 1-uu PC + 1 uuu0 0uuu ---- u-uu 000h 000x xuuu ---- 1-u0 uuu1 0uuu ---- u-uu Condition WDT Wake-up Brown-out Detect Reset (1) Interrupt Wake-up from SLEEP PC + 1 Legend: u = unchanged,
PIC16F62X FIGURE 14-8: TIMEOUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE VDD MCLR INTERNAL POR Tpwrt PWRT TIMEOUT Tost OST TIMEOUT INTERNAL RESET TIMEOUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2 FIGURE 14-9: VDD MCLR INTERNAL POR Tpwrt PWRT TIMEOUT Tost OST TIMEOUT INTERNAL RESET FIGURE 14-10: TIMEOUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD) VDD MCLR INTERNAL POR Tpwrt PWRT TIMEOUT Tost OST TIMEOUT INTERNAL RESET 2003 Microchip Technology Inc.
PIC16F62X FIGURE 14-11: VDD EXTERNAL POWER-ON RESET CIRCUIT (FOR SLOW VDD POWER-UP) FIGURE 14-13: EXTERNAL BROWN-OUT PROTECTION CIRCUIT 2 VDD VDD VDD R1 Q1 D MCLR R R2 R1 40k PIC16F62X MCLR PIC16F62X C Note Note 1: External Power-on Reset circuit is required only if VDD power-up slope is too slow. The diode D helps discharge the capacitor quickly when VDD powers down. 2: R < 40 kΩ is recommended to make sure that voltage drop across R does not violate the device’s electrical specification.
PIC16F62X 14.6 Interrupts When an interrupt is responded to, the GIE is cleared to disable any further interrupt, the return address is pushed into the stack and the PC is loaded with 0004h. Once in the interrupt service routine the source(s) of the interrupt can be determined by polling the interrupt flag bits. The interrupt flag bit(s) must be cleared in software before re-enabling interrupts to avoid RB0/INT recursive interrupts.
PIC16F62X 14.6.1 RB0/INT INTERRUPT 14.6.2 TMR0 INTERRUPT An overflow (FFh → 00h) in the TMR0 register will set the T0IF (INTCON<2>) bit. The interrupt can be enabled/disabled by setting/clearing T0IE (INTCON<5>) bit. For operation of the Timer0 module, see Section 6.0. External interrupt on RB0/INT pin is edge triggered: either rising if INTEDG bit (OPTION<6>) is set, or falling, if INTEDG bit is clear. When a valid edge appears on the RB0/INT pin, the INTF bit (INTCON<1>) is set.
PIC16F62X TABLE 14-9: Address SUMMARY OF INTERRUPT REGISTERS Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 0Bh INTCON GIE PEIE T0IE INTE RBIE 0Ch PIR1 8Ch PIE1 EEIF EEIE CMIF CMIE RCIF RCIE TXIF TXIE — — Bit 2 Bit 1 Bit 0 T0IF INTF RBIF CCP1IF TMR2IF TMR1IF CCP1IE TMR2IE TMR1IE Value on POR Reset Value on all other RESETS(1) 0000 000x 0000 000u 0000 -000 0000 -000 0000 -000 0000 -000 Note 1: Other (non Power-up) Resets include MCLR Reset, Brown-out Detect Reset and Watchdog Timer R
PIC16F62X FIGURE 14-16: WATCHDOG TIMER BLOCK DIAGRAM From TMR0 Clock Source (Figure 6-1) 0 M U 1X Watchdog Timer WDT POSTSCALER/ TMR0 PRESCALER 8 8 to 1 MUX PSA 3 PS<2:0> WDT Enable Bit To TMR0 (Figure 6-1) 0 MUX 1 PSA WDT Timeout Note 1: T0SE, T0CS, PSA, PS0-PS2 are bits in the OPTION register. TABLE 14-10: SUMMARY OF WATCHDOG TIMER REGISTERS Address Name 2007h Config. bits 81h Legend: Note 1: 14.
PIC16F62X 14.9.1 WAKE-UP FROM SLEEP The device can wake-up from SLEEP through one of the following events: 1. 2. 3. External RESET input on MCLR pin Watchdog Timer Wake-up (if WDT was enabled) Interrupt from RB0/INT pin, RB Port change, or the Peripheral Interrupt (Comparator). The first event will cause a device RESET. The two latter events are considered a continuation of program execution. The TO and PD bits in the STATUS register can be used to determine the cause of device RESET.
PIC16F62X 14.12 In-Circuit Serial Programming 14.13 Low Voltage Programming The PIC16F62X microcontrollers can be serially programmed while in the end application circuit. This is simply done with two lines for clock and data, and three other lines for power, ground, and the programming voltage. This allows customers to manufacture boards with unprogrammed devices, and then program the microcontroller just before shipping the product.
PIC16F62X 15.0 INSTRUCTION SET SUMMARY Each PIC16F62X instruction is a 14-bit word divided into an OPCODE which specifies the instruction type and one or more operands which further specify the operation of the instruction. The PIC16F62X instruction set summary in Table 15-2 lists byte-oriented, bitoriented, and literal and control operations. Table 15-1 shows the opcode field descriptions.
PIC16F62X TABLE 15-2: PIC16F62X INSTRUCTION SET 14-Bit Opcode Mnemonic, Operands Description Cycles MSb LSb Status Affected Notes BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF f, d f, d f — f, d f, d f, d f, d f, d f, d f, d f — f, d f, d f, d f, d f, d Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f, Skip if 0 Increment f Increment f, Skip if 0 Inclusive OR W with f Move f Move
PIC16F62X 15.1 Instruction Descriptions ADDLW Add Literal and W Syntax: [ label ] ADDLW k ANDLW AND Literal with W Syntax: [ label ] ANDLW k Operands: 0 ≤ k ≤ 255 Operands: 0 ≤ k ≤ 255 Operation: (W) + k → (W) Operation: (W) .AND. (k) → (W) Status Affected: C, DC, Z Status Affected: Z Encoding: 11 Encoding: 11 Description: The contents of the W register are added to the eight bit literal 'k' and the result is placed in the W register.
PIC16F62X BCF Bit Clear f BTFSC Bit Test f, Skip if Clear Syntax: [ label ] BCF Syntax: [ label ] BTFSC f,b Operands: 0 ≤ f ≤ 127 0≤b≤7 Operands: 0 ≤ f ≤ 127 0≤b≤7 Operation: 0 → (f) Operation: skip if (f) = 0 Status Affected: None Status Affected: None f,b Encoding: 01 Description: Bit 'b' in register 'f' is cleared.
PIC16F62X BTFSS Bit Test f, Skip if Set CALL Call Subroutine Syntax: [ label ] BTFSS f,b Syntax: [ label ] CALL k Operands: 0 ≤ f ≤ 127 0≤b<7 Operands: 0 ≤ k ≤ 2047 Operation: (PC)+ 1→ TOS, k → PC<10:0>, (PCLATH<4:3>) → PC<12:11> Status Affected: None Encoding: 10 Description: Call Subroutine. First, return address (PC+1) is pushed onto the stack. The eleven bit immediate address is loaded into PC bits <10:0>. The upper bits of the PC are loaded from PCLATH.
PIC16F62X CLRW Clear W COMF Complement f Syntax: [ label ] CLRW Syntax: [ label ] COMF Operands: None Operands: Operation: 00h → (W) 1→Z 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (f) → (dest) Z Status Affected: Z Status Affected: Encoding: 00 Description: W register is cleared. Zero bit (Z) is set. Words: 1 Cycles: 1 Example f,d Encoding: 00 Description: The contents of register 'f' are complemented. If 'd' is 0 the result is stored in W.
PIC16F62X DECFSZ Decrement f, Skip if 0 GOTO Unconditional Branch Syntax: [ label ] DECFSZ f,d Syntax: 0 ≤ f ≤ 127 d ∈ [0,1] [ label ] Operands: Operands: 0 ≤ k ≤ 2047 Operation: k → PC<10:0> PCLATH<4:3> → PC<12:11> Status Affected: None Operation: (f) - 1 → (dest); 0 Status Affected: None Encoding: 00 Description: The contents of register 'f' are decremented. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is placed back in register 'f'.
PIC16F62X INCF Increment f INCFSZ Increment f, Skip if 0 Syntax: [ label ] Syntax: [ label ] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (f) + 1 → (dest) Operation: (f) + 1 → (dest), skip if result = 0 Status Affected: Z Status Affected: None INCF f,d Encoding: 00 Description: The contents of register 'f' are incremented. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is placed back in register 'f'.
PIC16F62X IORLW Inclusive OR Literal with W MOVLW Move Literal to W Syntax: [ label ] Syntax: [ label ] IORLW k MOVLW k Operands: 0 ≤ k ≤ 255 Operands: 0 ≤ k ≤ 255 Operation: (W) .OR. k → (W) Operation: k → (W) Status Affected: Z Status Affected: None Encoding: 11 Encoding: 11 Description: The contents of the W register is OR’ed with the eight bit literal 'k'. The result is placed in the W register. Description: The eight bit literal 'k' is loaded into W register.
PIC16F62X MOVWF Move W to f OPTION Load Option Register Syntax: [ label ] Syntax: [ label ] 0 ≤ f ≤ 127 Operands: None Operands: Operation: (W) → (f) Operation: (W) → OPTION Status Affected: None Status Affected: None Encoding: 00 Encoding: 00 Description: The contents of the W register are loaded in the OPTION register. This instruction is supported for code compatibility with PIC16C5X products. Since OPTION is a readable/writable register, the user can directly address it.
PIC16F62X RETLW Return with Literal in W RLF Rotate Left f through Carry Syntax: [ label ] Syntax: [ label ] Operands: 0 ≤ k ≤ 255 Operands: Operation: k → (W); TOS → PC 0 ≤ f ≤ 127 d ∈ [0,1] Operation: See description below Status Affected: None Status Affected: C Encoding: 11 Encoding: 00 Description: The W register is loaded with the eight bit literal 'k'. The program counter is loaded from the top of the stack (the return address). This is a two-cycle instruction.
PIC16F62X RRF Rotate Right f through Carry SUBLW Subtract W from Literal Syntax: [ label ] Syntax: [ label ] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operands: 0 ≤ k ≤ 255 Operation: k - (W) → (W) Operation: See description below C Status Affected: C, DC, Z Status Affected: Encoding: 11 Description: The W register is subtracted (2’s complement method) from the eight bit literal 'k'. The result is placed in the W register.
PIC16F62X SUBWF Subtract W from f SWAPF Swap Nibbles in f Syntax: [ label ] Syntax: [ label ] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (f) - (W) → (dest) Operation: Status Affected: C, DC, Z (f<3:0>) → (dest<7:4>), (f<7:4>) → (dest<3:0>) Status Affected: None Encoding: 00 Encoding: 00 Description: Subtract (2’s complement method) W register from register 'f'. If 'd' is 0 the result is stored in the W register.
PIC16F62X XORLW Exclusive OR Literal with W XORWF Exclusive OR W with f Syntax: [ label ] Syntax: [ label ] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (W) .XOR. (f) → (dest) Status Affected: Z XORLW k Operands: 0 ≤ k ≤ 255 Operation: (W) .XOR. k → (W) Status Affected: Z Encoding: 11 Description: The contents of the W register are XOR’ed with the eight bit literal 'k'. The result is placed in the W register.
Device# 16.0 DEVELOPMENT SUPPORT 16.
Device# 16.3 MPLAB C17 and MPLAB C18 C Compilers 16.6 The MPLAB C17 and MPLAB C18 Code Development Systems are complete ANSI C compilers for Microchip’s PIC17CXXX and PIC18CXXX family of microcontrollers. These compilers provide powerful integration capabilities, superior code optimization and ease of use not found with other compilers. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. 16.
Device# 16.9 MPLAB ICE 2000 High Performance Universal In-Circuit Emulator 16.11 MPLAB ICD 2 In-Circuit Debugger The MPLAB ICE 2000 universal in-circuit emulator is intended to provide the product development engineer with a complete microcontroller design tool set for PICmicro microcontrollers. Software control of the MPLAB ICE 2000 in-circuit emulator is advanced by the MPLAB Integrated Development Environment, which allows editing, building, downloading and source debugging from a single environment.
Device# 16.14 PICDEM 1 PICmicro Demonstration Board 16.16 PICDEM 2 Plus Demonstration Board The PICDEM 1 demonstration board demonstrates the capabilities of the PIC16C5X (PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X, PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and PIC17C44. All necessary hardware and software is included to run basic demo programs.
Device# 16.19 PICDEM 18R PIC18C601/801 Demonstration Board 16.21 PICDEM USB PIC16C7X5 Demonstration Board The PICDEM 18R demonstration board serves to assist development of the PIC18C601/801 family of Microchip microcontrollers. It provides hardware implementation of both 8-bit Multiplexed/De-multiplexed and 16-bit Memory modes. The board includes 2 Mb external FLASH memory and 128 Kb SRAM memory, as well as serial EEPROM, allowing access to the wide range of memory types supported by the PIC18C601/801.
DS40300C-page 126 Software Tools Programmers Debugger Emulators PIC16C6X PIC16CXXX PIC16C43X PIC16F62X PIC16C7X PIC16C7XX PIC16C7X5 PIC16C8X PIC16F8XX PIC16C9XX Preliminary PRO MATE II Universal Device Programmer ** ** ** * Contact the Microchip web site at www
PIC16F62X 17.0 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings† Ambient temperature under bias................................................................................................................. -40 to +125°C Storage temperature .............................................................................................................................. -65°C to +150°C Voltage on VDD with respect to VSS .......................................................................................
PIC16F62X PIC16F62X VOLTAGE-FREQUENCY GRAPH, 0°C ≤ TA ≤ +70°C FIGURE 17-1: 6.0 5.5 5.0 VDD (VOLTS) 4.5 4.0 3.5 3.0 2.5 0 4 10 20 25 FREQUENCY (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. PIC16F62X VOLTAGE-FREQUENCY GRAPH, -40°C ≤ TA < 0°C, +70°C < TA ≤ 85°C FIGURE 17-2: 6.0 5.5 5.0 VDD (VOLTS) 4.5 4.0 3.5 3.0 2.5 2.0 0 4 10 20 25 FREQUENCY (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
PIC16F62X PIC16LF62X VOLTAGE-FREQUENCY GRAPH, 0°C ≤ TA ≤ +70°C FIGURE 17-3: 6.0 5.5 5.0 VDD (VOLTS) 4.5 4.0 3.5 3.0 2.5 2.0 0 4 10 20 25 FREQUENCY (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. FIGURE 17-4: PIC16LF62X VOLTAGE-FREQUENCY GRAPH, -40°C ≤ TA < 0°C, +70°C < TA ≤ 85°C 6.0 5.5 5.0 VDD (VOLTS) 4.5 4.0 3.5 3.0 2.5 2.
PIC16F62X 17.
PIC16F62X 17.
PIC16F62X 17.2 DC Characteristics: PIC16F62X (Commercial, Industrial, Extended) PIC16LF62X (Commercial, Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial and 0°C ≤ TA ≤ +70°C for commercial and -40°C ≤ TA ≤ +125°C for extended Operating voltage VDD range as described in DC spec Table 17-1 and Table 17-2 DC CHARACTERISTICS Param. No. Sym VIL Characteristic/Device Min Typ† Max Unit VSS — VSS VSS — 0.8 0.15 VDD 0.2 VDD 0.
PIC16F62X TABLE 17-1: COMPARATOR SPECIFICATIONS Operating Conditions: 3.0V < VDD <5.5V, -40°C < TA < +125°C, unless otherwise stated. Param No. Characteristics Sym Min Typ Max Units VIOFF — ±5.0 ±10 mV D300 Input offset voltage D301* Input Common mode voltage VICM 0 — VDD - 1.
PIC16F62X 17.3 Timing Parameter Symbology The timing parameter symbols have been created with one of the following formats: 1. TppS2ppS 2.
PIC16F62X TABLE 17-3: DC CHARACTERISTICS: PIC16F62X, PIC16LF62X DC Characteristics Standard Operating Conditions (unless otherwise stated) Parameter Sym No. D120 D121 ED VDRW D122 TDEW D130 D131 EP VPR D132 D133 Characteristic Data EEPROM Memory Endurance VDD for read/write Erase/Write cycle time Program FLASH Memory Endurance VDD for read Min Typ† Max 1M* VMIN 10M — — 5.5 — 4 8* 1000* Vmin 10000 — — 5.5 — 4 5.5 8* 4.
PIC16F62X TABLE 17-4: Param No. EXTERNAL CLOCK TIMING REQUIREMENTS Sym Characteristic Fosc External CLKIN Frequency(1) Min Typ† Max DC — 4 DC DC — — 20 200 — — — — 4 37 4.00 4 4 20 200 4.28 Oscillator Frequency(1) 0.1 1 3.65 4 5 1 INTRC Internal Calibrated RC 3.65 ER External Biased ER Frequency 10 kHz Tosc External CLKIN Period(1) 250 50 5 Oscillator Period(1) 2 3 * 250 250 50 5 Tcy Instruction Cycle Time 1.
PIC16F62X FIGURE 17-7: CLKOUT AND I/O TIMING Q1 Q4 Q2 Q3 OSC1 11 10 22 CLKOUT 23 13 19 14 12 18 16 I/O PIN (INPUT) 15 17 I/O PIN (OUTPUT) NEW VALUE OLD VALUE 20, 21 TABLE 17-5: Param No.
PIC16F62X FIGURE 17-8: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Timeout 32 OSC Timeout Internal RESET Watchdog Timer RESET 31 34 34 I/O Pins FIGURE 17-9: BROWN-OUT DETECT TIMING VBOD VDD 35 TABLE 17-6: Param No.
PIC16F62X FIGURE 17-10: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS RA4/T0CKI 41 40 42 RB6/T1OSO/T1CKI 46 45 47 48 TMR0 OR TMR1 2003 Microchip Technology Inc.
PIC16F62X TABLE 17-7: Param No.
PIC16F62X TABLE 17-8: CAPTURE/COMPARE/PWM REQUIREMENTS Param Sym No. Characteristic 50* No Prescaler TccL CCP input low time 51* TccH CCP input high time Min Typ† Max Units 0.5TCY + 20 16F62X With Prescaler 16LF62X No Prescaler — — ns 10 — — ns 20 — — ns 0.
PIC16F62X NOTES: DS40300C-page 142 Preliminary 2003 Microchip Technology Inc.
PIC16F62X 18.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES In some graphs or tables, the data presented is outside specified operating range (i.e., outside specified VDD range). This is for information only and devices are ensured to operate properly only within the specified range. The data presented in this section is a statistical summary of data collected on units from different lots over a period of time and matrix samples. 'Typical' represents the mean of the distribution at 25°C. 'max or min.
PIC16F62X . Note: The graphs and tables provided in this section are for design guidance and are not tested. FIGURE 18-2: MAXIMUM IDD VS FOSC OVER VDD (HS MODE) Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to 125°C) Minimum: mean – 3σ (-40°C to 125°C) Maximum IDD vs FOSC over VDD (HS mode) 7 6 5 IDD (mA) 5.5V 4 5.0V 3 4.5V 4.
PIC16F62X . Note: The graphs and tables provided in this section are for design guidance and are not tested. FIGURE 18-4: TYPICAL IDD VS FOSC OVER VDD (XT MODE) Typical: statistical mean @ 25°C PIC 16LF628 Maximum: mean + 3σ (-40°C to 125°C) Minimum: mean – 3σ (-40°C to 125°C) Typical I DD vs F O SC over V DD (XT m ode) 1.2 1.0 0.8 IDD (mA) 5.5V 5.0V 0.6 4.5V 4.0V 0.4 3.5V 3.0V 2.5V 0.2 2.0V 0.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.
PIC16F62X Note: The graphs and tables provided in this section are for design guidance and are not tested. FIGURE 18-6: MAXIMUM IDD VS FOSC OVER VDD (LP MODE) Typical: statistical mean @ 25°C Maximum: meanPIC16LF628 + 3σ (-40°C to 125°C) Minimum: mean – 3σ (-40°C to 125°C) Maximum I DD vs F OSC over V DD (LP m ode) 120.00 100.00 80.00 5.5V IDD (uA) 5.0V 60.00 4.5V 4.0V 40.00 3.5V 3.0V 20.00 0.00 30.000 2.5V 40.000 50.000 60.000 70.000 80.000 90.000 100.
PIC16F62X Note: The graphs and tables provided in this section are for design guidance and are not tested. FIGURE 18-8: TYPICAL INTERNAL RC FOSC VS VDD TEMPERATURE (-40 TO 125°C) INTERNAL 4 MHz OSCILLATOR Typical Internal RC FOSC vs VDD over Temperature (-40 to 125 C) Internal 4 MHz Oscillator Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to 125°C) Minimum: mean – 3σ (-40°C to 125°C) 4.1 125 C 85 C 25 C 4.0 FOSC (MHz) 3.9 -40 C 3.8 3.7 3.6 3.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
PIC16F62X Note: The graphs and tables provided in this section are for design guidance and are not tested. FIGURE 18-10: IPD VS VDD SLEEP MODE, ALL PERIPHERALS DISABLED Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to 125°C) Minimum: mean – 3σ (-40°C to 125°C) IPD vs VDD Sleep mode, all peripherals disabled 4.0 Max (125C) IPD (uA) 3.0 2.0 1.0 Max (85C) Typ (25C) 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
PIC16F62X Note: The graphs and tables provided in this section are for design guidance and are not tested. FIGURE 18-12: ∆lTMR1OSC VS VDD OVER TEMP (0C to +70°C) SLEEP MODE, TIMER1 OSCILLATOR, 32 kHz XTAL Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to 125°C) Minimum: mean – 3σ (-40°C to 125°C) ∆ITMR1OSC vs VDD over Temp (0C to +70C) Sleep mode, Timer1 oscillator, 32 kHz XTAL 90 80 70 ∆ITMR1OSC (uA) 60 50 Max 40 Typ (25C) 30 20 10 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
PIC16F62X Note: The graphs and tables provided in this section are for design guidance and are not tested. ∆lCOMP VS VDD SLEEP MODE, COMPARATORS ENABLED FIGURE 18-14: Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to 125°C) Minimum: mean – 3σ (-40°C to 125°C) ∆ICOMP vs VDD Sleep mode, Comparators enabled 140.0 120.0 ∆ICOMP (uA) 100.0 80.0 Max (125C) Typ (25C) 60.0 40.0 20.0 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
PIC16F62X Note: The graphs and tables provided in this section are for design guidance and are not tested. FIGURE 18-16: MINIMUM, TYPICAL and MAXIMUM WDT PERIOD VS VDD (-40°C to +125°C) Minimum, Typical and Maximum WDT Period vs V DD (-40C to +125C) Typical: statistical mean @ 25°C PIC16LF228 Maximum: mean + 3σ (-40°C to 125°C) Minimum: mean – 3σ (-40°C to 125°C) 45 40 35 WDT Period (mS) 30 Max 125C Max 85C 25 20 Typ 25C 15 Min -40C 10 5 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
PIC16F62X Note: The graphs and tables provided in this section are for design guidance and are not tested. FIGURE 18-18: VOH VS IOH OVER TEMP (C) VDD = 5V Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to 125°C) Minimum: mean – 3σ (-40°C to 125°C) VOH vs IOH over Temp (C) VDD = 5V 5.0 4.5 4.0 3.5 Max (-40C) VOH (V) 3.0 Typ (25C) 2.5 2.0 1.5 Min (125C) 1.0 0.5 0.0 0.0 5.0 10.0 15.0 20.0 25.
PIC16F62X Note: The graphs and tables provided in this section are for design guidance and are not tested. FIGURE 18-20: VOL VS IOL OVER TEMP (C) VDD = 5V Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to 125°C) Minimum: mean – 3σ (-40°C to 125°C) VOL vs IOL over Temp (C) VDD = 5V 0.80 0.70 Max (125C) 0.60 VOL (V) 0.50 Typ (25C) 0.40 Min (-40C) 0.30 0.20 0.10 0.00 0.0 5.0 10.0 15.0 20.0 25.
PIC16F62X Note: The graphs and tables provided in this section are for design guidance and are not tested. FIGURE 18-22: VIN VS VDD TTL Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to 125°C) Minimum: mean – 3σ (-40°C to 125°C) VIN vs VDD TTL Input 2.0 1.5 Max (-40C) Vin (V) Min (125C) 1.0 0.5 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
PIC16F62X Note: The graphs and tables provided in this section are for design guidance and are not tested. FIGURE 18-24: MAXIMUM IDD VS VDD OVER TEMPERATURE (-40 TO +125°C) INTERNAL 37 kHz OSCILLATOR Typical: statistical PIC16LF628 mean @ 25°C Maximum: mean + 3σ (-40°C to 125°C) Minimum: mean – 3σ (-40°C to 125°C) Maximum IDD vs V DD over Temperature (-40 to +125 C) Internal 37kHz Oscillator 35.000 30.000 125 C IDD (µA) 25.000 85 25 C 20.000 -40 C 15.000 10.000 2.5 3.0 3.5 4.0 4.5 5.0 5.
PIC16F62X Note: The graphs and tables provided in this section are for design guidance and are not tested. FIGURE 18-26: MAXIMUM IDD VS VDD OVER TEMPERATURE (-40 TO +125°C) INTERNAL 4 MHz OSCILLATOR Typical: statistical mean @ 25°C PIC16LF628 Maximum: mean + 3σ (-40°C to 125°C) Minimum: mean – 3σ (-40°C to 125°C) Maximum IDD vs V DD over Temperature (-40 to +125 C) Internal 4MHz Oscillator 1.30 1.20 1.10 IDD (mA) 1.00 0.90 125 0.80 85 25 C -40 C 0.70 0.60 0.50 0.40 2.5 3.0 3.5 4.0 4.
PIC16F62X 19.0 PACKAGING INFORMATION 19.1 Package Marking Information EXAMPLE 18-LEAD PDIP XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN 18-LEAD SOIC (.300") PIC16F628/P 9917017 EXAMPLE XXXXXXXXXXXX XXXXXXXXXXXX XXXXXXXXXXXX PIC16F628/SO YYWWNNN 20-LEAD SSOP EXAMPLE XXXXXXXXXX XXXXXXXXXX PIC16F628/SO YYWWNNN 9910017 Legend: MM...M XX...
PIC16F62X K04-007 18-Lead Plastic Dual In-line (P) – 300 mil E1 D 2 n α 1 E A2 A L c A1 B1 β p B eB Units Dimension Limits n p MIN INCHES* NOM 18 .100 .155 .130 MAX MILLIMETERS NOM 18 2.54 3.56 3.94 2.92 3.30 0.38 7.62 7.94 6.10 6.35 22.61 22.80 3.18 3.30 0.20 0.29 1.14 1.46 0.36 0.46 7.87 9.40 5 10 5 10 MIN Number of Pins Pitch Top to Seating Plane A .140 .170 Molded Package Thickness A2 .115 .145 Base to Seating Plane .015 A1 Shoulder to Shoulder Width E .300 .313 .
PIC16F62X K04-051 18-Lead Plastic Small Outline (SO) – Wide, 300 mil E p E1 D 2 B n 1 h α 45° c A2 A φ β L Units Dimension Limits n p Number of Pins Pitch Overall Height Molded Package Thickness Standoff § Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom A A2 A1 E E1 D h L φ c B α β MIN .093 .088 .004 .394 .291 .446 .010 .016 0 .009 .014 0 0 A1 INCHES* NOM 18 .050 .099 .091 .
PIC16F62X K04-072 20-Lead Plastic Shrink Small Outline (SS) – 5.30 mm E E1 p D B 2 1 n α c A2 A φ L A1 β Units Dimension Limits n p Number of Pins Pitch Overall Height Molded Package Thickness Standoff § Overall Width Molded Package Width Overall Length Foot Length Lead Thickness Foot Angle Lead Width Mold Draft Angle Top Mold Draft Angle Bottom A A2 A1 E E1 D L c φ B α β MIN .068 .064 .002 .299 .201 .278 .022 .004 0 .010 0 0 INCHES* NOM 20 .026 .073 .068 .006 .309 .207 .284 .030 .007 4 .
PIC16F62X INDEX A A/D Special Event Trigger (CCP)....................................... 63 Absolute Maximum Ratings .............................................. 127 ADDLW Instruction ........................................................... 109 ADDWF Instruction ........................................................... 109 ANDLW Instruction ........................................................... 109 ANDWF Instruction ...........................................................
PIC16F62X MOVLW..................................................................... 115 MOVWF .................................................................... 116 NOP .......................................................................... 116 OPTION .................................................................... 116 RETFIE ..................................................................... 116 RETLW...................................................................... 117 RETURN .............
PIC16F62X T1SYNC bit ......................................................................... 46 T2CKPS0 bit ....................................................................... 51 T2CKPS1 bit ....................................................................... 51 Timer0 TIMER0 (TMR0) Interrupt ........................................... 43 TIMER0 (TMR0) Module............................................. 43 TMR0 with External Clock...........................................
PIC16F62X NOTES: DS40300C-page 164 Preliminary 2003 Microchip Technology Inc.
PIC16F62X ON-LINE SUPPORT Microchip provides on-line support on the Microchip World Wide Web site. The web site is used by Microchip as a means to make files and information easily available to customers. To view the site, the user must have access to the Internet and a web browser, such as Netscape® or Microsoft® Internet Explorer. Files are also available for FTP download from our FTP site.
PIC16F62X READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document.
PIC16F62X PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. -XX X Device Frequency Range Temperature Range /XX XXX Package Pattern Standard VDD range 3.0V to 5.5V VDD range 3.0V to 5.5V (Tape and Reel) VDD range 2.0V to 5.5V VDD range 2.0V to 5.
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