Datasheet
© 2009 Microchip Technology Inc. DS41288F-page 69
PIC16F610/616/16HV610/616
REGISTER 8-4: SRCON0: SR LATCH CONTROL 0 REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/S-0 R/S-0 U-0 R/W-0
SR1
(2)
SR0
(2)
C1SEN C2REN PULSS PULSR — SRCLKEN
bit 7 bit 0
Legend: S = Bit is set only -
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 SR1: SR Latch Configuration bit
(2)
1 = C2OUT pin is the latch Q output
0 = C2OUT pin is the C2 comparator output
bit 6 SR0: SR Latch Configuration bits
(2)
1 = C1OUT pin is the latch Q output
0 = C1OUT pin is the C1 Comparator output
bit 5 C1SEN: C1 Set Enable bit
1 = C1 comparator output sets SR latch
0 = C1 comparator output has no effect on SR latch
bit 4 C2REN: C2 Reset Enable bit
1 = C2 comparator output resets SR latch
0 = C2 comparator output has no effect on SR latch
bit 3 PULSS: Pulse the SET Input of the SR Latch bit
1 = Triggers pulse generator to set SR latch. Bit is immediately reset by hardware.
0 = Does not trigger pulse generator
bit 2 PULSR: Pulse the Reset Input of the SR Latch bit
1 = Triggers pulse generator to reset SR latch. Bit is immediately reset by hardware.
0 = Does not trigger pulse generator
bit 1 Unimplemented: Read as ‘0’
bit 0 SRCLKEN: SR Latch Set Clock Enable bit
1 = Set input of SR latch is pulsed with SRCLK
0 = Set input of SR latch is not pulsed with the SRCLK
Note 1: The C1OUT and C2OUT bits in the CMxCON0 register will always reflect the actual comparator output (not the level on
the pin), regardless of the SR latch operation.
2: To enable an SR Latch output to the pin, the appropriate CxOE, and TRIS bits must be properly configured.
REGISTER 8-5: SRCON1: SR LATCH CONTROL 1 REGISTER
R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0
SRCS1 SRCS0
— — — — — —
bit 7 bit 0
Legend: S = Bit is set only -
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-6 SRCS<1:0>: SR Latch Clock Prescale bits
00 = F
OSC/16
01 = F
OSC/32
10 = F
OSC/64
11 = F
OSC/128
bit 5-0 Unimplemented: Read as ‘0’