Datasheet

PIC16F610/616/16HV610/616
DS41288F-page 68 © 2009 Microchip Technology Inc.
8.10 Comparator SR Latch
The SR latch module provides additional control of the
comparator outputs. The module consists of a single
SR latch and output multiplexers. The SR latch can be
set, reset or toggled by the comparator outputs. The SR
latch may also be set or reset, independent of
comparator output, by control bits in the SRCON0
control register. The SR latch output multiplexers select
whether the latch outputs or the comparator outputs are
directed to the I/O port logic for eventual output to a pin.
The SR latch also has a variable clock, which is
connected to the set input of the latch. The SRCLKEN
bit of SRCON0 enables the SR latch set clock. The
clock will periodically pulse the set input of the latch.
Control over the frequency of the SR latch set clock is
provided by the SRCS<1:0> bits of SRCON1 register.
8.10.1 LATCH OPERATION
The latch is a Set-Reset latch that does not depend on a
clock source. Each of the Set and Reset inputs are
active-high. Each latch input is connected to a
comparator output and a software controlled pulse
generator. The latch can be set by C1OUT or the PULSS
bit of the SRCON0 register. The latch can be reset by
C2OUT or the PULSR bit of the SRCON0 register. The
latch is reset-dominant, therefore, if both Set and Reset
inputs are high the latch will go to the Reset state. Both
the PULSS and PULSR bits are self resetting which
means that a single write to either of the bits is all that is
necessary to complete a latch Set or Reset operation.
8.10.2 LATCH OUTPUT
The SR<1:0> bits of the SRCON0 register control the
latch output multiplexers and determine four possible
output configurations. In these four configurations, the
CxOUT I/O port logic is connected to:
• C1OUT and C2OUT
• C1OUT and SR latch Q
• C2OUT and SR latch Q
• SR latch Q and Q
After any Reset, the default output configuration is the
unlatched C1OUT and C2OUT mode. This maintains
compatibility with devices that do not have the SR latch
feature.
The applicable TRIS bits of the corresponding ports
must be cleared to enable the port pin output drivers.
Additionally, the CxOE comparator output enable bits of
the CMxCON0 registers must be set in order to make the
comparator or latch outputs available on the output pins.
The latch configuration enable states are completely
independent of the enable states for the comparators.
FIGURE 8-8: SR LATCH SIMPLIFIED BLOCK DIAGRAM
C1SEN
SR0
PULSS
S
R
Q
Q
C2REN
PULSR
SR1
Note 1: If R = 1 and S = 1 simultaneously, Q = 0, Q = 1
2: Pulse generator causes a 1 T
OSC pulse width.
3: Output shown for reference only. See I/O port pin block diagram for more detail.
Pulse
Gen
(2)
Pulse
Gen
(2)
SYNCC2OUT (from comparator)
C1OUT (from comparator)
C2OE
C2OUT pin
(3)
C1OE
C1OUT pin
(3)
0
1
MUX
1
0
MUX
SR
Latch
(1)
SRCLKEN
SRCLK