Datasheet

ManualsBrandsMICROCHIP TECHNOLOGY ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller SOIC 14 8-Bit 20 MHz I/O number 11

PIC16F610/616/16HV610/616

TABLE 2-2: PIC16F610/616/16HV610/616 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on

POR, BOR

Page

Bank 1

80h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 24, 116

81h OPTION_REG RAPU

INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 19, 116

82h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 24, 116

83h STATUS IRP

(1)

RP1

(1)

RP0 TO PD ZDCC0001 1xxx 18, 116

84h FSR Indirect Data Memory Address Pointer xxxx xxxx 24, 116

85h TRISA

— — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 33, 116

86h — Unimplemented — —

87h TRISC

— — TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 --11 1111 42, 116

88h — Unimplemented — —

89h — Unimplemented — —

8Ah PCLATH

— — — Write Buffer for upper 5 bits of Program Counter ---0 0000 24, 116

8Bh INTCON GIE PEIE T0IE INTE RAIE T0IF INTF RAIF 0000 0000 20, 116

8Ch PIE1

—ADIE

(3)

CCP1IE

(3)

C2IE C1IE —TMR2IE

(3)

TMR1IE -000 0-00 21, 116

8Dh — Unimplemented — —

8Eh PCON

— — — — — —PORBOR ---- --qq 23, 116

8Fh — Unimplemented — —

90h OSCTUNE

— — — TUN4 TUN3 TUN2 TUN1 TUN0 ---0 0000 31, 117

91h ANSEL ANS7 ANS6 ANS5 ANS4 ANS3

(3)

ANS2

(3)

ANS1 ANS0 1111 1111 34, 117

92h PR2

(3)

Timer2 Module Period Register 1111 1111 55, 117

93h — Unimplemented — —

94h — Unimplemented — —

95h WPUA

— — WPUA5 WPUA4 — WPUA2 WPUA1 WPUA0 --11 -111 35, 117

96h IOCA

— — IOCA5 IOCA4 IOCA3 IOCA2 IOCA1 IOCA0 --00 0000 35, 117

97h — Unimplemented — —

98h — Unimplemented — —

99h SRCON0 SR1 SR0 C1SEN C2REN PULSS PULSR

— SRCLKEN 0000 00-0 69, 117

9Ah SRCON1 SRCS1 SRCS0

— — — — — — 00-- ---- 69, 117

9Bh — Unimplemented — —

9Ch — Unimplemented — —

9Dh — Unimplemented — —

9Eh ADRESL

(3,4)

Least Significant 2 bits of the left shifted result or 8 bits of the right shifted result xxxx xxxx 80, 117

9Fh ADCON1

(3)

— ADCS2 ADCS1 ADCS0 — — — — -000 ---- 79, 117

Legend: – = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented

Note 1: IRP and RP1 bits are reserved, always maintain these bits clear.

2: RA3 pull-up is enabled when MCLRE is ‘1’ in the Configuration Word register.

3: PIC16F616/16HV616 only.

4: Read-only Register.