PIC16F610/16HV610 PIC16F616/16HV616 Data Sheet 14-Pin, Flash-Based 8-Bit CMOS Microcontrollers © 2009 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
PIC16F610/616/16HV610/616 14-Pin Flash-Based, 8-Bit CMOS Microcontrollers High-Performance RISC CPU: Peripheral Features: • Only 35 Instructions to Learn: - All single-cycle instructions except branches • Operating Speed: - DC – 20 MHz oscillator/clock input - DC – 200 ns instruction cycle • Interrupt Capability • 8-Level Deep Hardware Stack • Direct, Indirect and Relative Addressing modes • Shunt Voltage Regulator (PIC16HV610/616 only): - 5 volt regulation - 4 mA to 50 mA shunt range • 11 I/O Pins and 1
PIC16F610/616/16HV610/616 Program Memory Data Memory Flash (words) SRAM (bytes) PIC16F610 1024 PIC16HV610 1024 PIC16F616 PIC16HV616 Device I/O 10-bit A/D (ch) Comparators Timers 8/16-bit 64 11 — 2 1/1 2.0-5.5V 64 11 — 2 1/1 2.0-user defined 2048 128 11 8 2 2/1 2.0-5.5V 2048 128 11 8 2 2/1 2.
PIC16F610/616/16HV610/616 VDD 1 RA5/T1CKI/OSC1/CLKIN 2 RA4/AN3/T1G/OSC2/CLKOUT 3 RA3/MCLR/VPP 4 RC5/CCP1/P1A 5 RC4/C2OUT/P1B RC3/AN7/C12IN3-/P1C 6 7 PIC16F616/16HV616 PIC16F616/16HV616 14-Pin Diagram (PDIP, SOIC, TSSOP) 14 VSS 13 RA0/AN0/C1IN+/ICSPDAT 12 RA1/AN1/C12IN0-/VREF/ICSPCLK 11 RA2/AN2/T0CKI/INT/C1OUT 10 RC0/AN4/C2IN+ 9 RC1/AN5/C12IN1- 8 RC2/AN6/C12IN2-/P1D PIC16F616/16HV616 14-PIN SUMMARY TABLE 2: I/O Pin Analog Comparators Timer CCP Interrupts Pull-ups Basic
PIC16F610/616/16HV610/616 VDD NC NC VSS 15 14 13 11 RA1/C12IN0-/ICSPCLK 10 RA2/T0CKI/INT/C1OUT 8 9 7 4 RA0/C1IN+/ICSPDAT RC1/C12IN1- RC5 6 3 12 RC2/C12IN2- RA3/MCLR/VPP PIC16F610/ PIC16HV610 5 2 RC3/C12IN3- RA4/T1G/OSC2/CLKOUT RC4/C2OUT 1 RC0/C2IN1+ PIC16F610/16HV610 16-PIN SUMMARY TABLE 3: I/O RA5/T1CKI/OSC1/CLKIN 16 PIC16F610/16HV610 16-Pin Diagram (QFN) Pin Comparators Timers Interrupts Pull-ups Basic 12 C1IN+ — IOC Y ICSPDAT RA1 11 C12IN0- — IOC Y ICSP
PIC16F610/616/16HV610/616 VDD NC NC VSS 15 14 13 RA2/AN2/T0CKI/INT/C1OUT 9 8 4 10 RC1/AN5/C12IN1- RC5/CCP/P1A RA1/AN1/C12IN0-/VREF/ICSPCLK 7 3 11 RC2/AN6/C12IN2-/P1D RA3/MCLR/VPP PIC16F616/ PIC16HV616 6 2 RA0/AN0/C1IN+/ICSPDAT RC3/AN7/C12IN3-/P1C RA4/AN3/T1G/OSC2/CLKOUT 12 5 1 RC4/C2OUT/P1B RA5/T1CKI/OSC1/CLKIN 16 PIC16F616/16HV616 16-Pin Diagram (QFN) RC0/AN4/C2IN1+ PIC16F616/16HV616 16-PIN SUMMARY TABLE 4: I/O Pin Analog Comparators Timers CCP Interrupts Pull-ups
PIC16F610/616/16HV610/616 Table of Contents 1.0 Device Overview .......................................................................................................................................................................... 9 2.0 Memory Organization ................................................................................................................................................................ 13 3.0 Oscillator Module .................................................................
PIC16F610/616/16HV610/616 1.0 DEVICE OVERVIEW The PIC16F610/616/16HV610/616 is covered by this data sheet. It is available in 14-pin PDIP, SOIC, TSSOP and 16-pin QFN packages.
PIC16F610/616/16HV610/616 FIGURE 1-2: PIC16F616/16HV616 BLOCK DIAGRAM INT Configuration 13 Flash 2K X 14 Program Memory Program Bus PORTA RA0 RA1 RA2 RA3 RA4 RA5 RAM 128 Bytes File Registers 8-Level Stack (13-Bit) 14 8 Data Bus Program Counter RAM Addr 9 Addr MUX Instruction Reg 7 Direct Addr Indirect Addr 8 PORTC RC0 RC1 RC2 RC3 RC4 RC5 FSR Reg STATUS Reg 8 3 Power-up Timer Instruction Decode and Control Timing Generation OSC1/CLKIN OSC2/CLKOUT MUX Oscillator Start-up Timer Power-on
PIC16F610/616/16HV610/616 TABLE 1-1: PIC16F610/16HV610 PINOUT DESCRIPTION Name RA0/C1IN+/ICSPDAT RA1/C12IN0-/ICSPCLK RA2/T0CKI/INT/C1OUT RA3/MCLR/VPP RA4/T1G/OSC2/CLKOUT RA5/T1CKI/OSC1/CLKIN RC0/C2IN+ RC1/C12IN1RC2/C12IN2RC3/C12IN3RC4/C2OUT Function Input Type Output Type Description RA0 TTL CMOS C1IN+ AN — PORTA I/O with prog. pull-up and interrupt-on-change ICSPDAT ST CMOS Serial Programming Data I/O PORTA I/O with prog.
PIC16F610/616/16HV610/616 TABLE 1-2: PIC16F616/16HV616 PINOUT DESCRIPTION Name RA0/AN0/C1IN+/ICSPDAT RA1/AN1/C12IN0-/VREF/ICSPCLK RA2/AN2/T0CKI/INT/C1OUT RA3/MCLR/VPP RA4/AN3/T1G/OSC2/CLKOUT RA5/T1CKI/OSC1/CLKIN RC0/AN4/C2IN+ RC1/AN5/C12IN1- RC2/AN6/C12IN2-/P1D RC3/AN7/C12IN3-/P1C RC4/C2OUT/P1B Function Input Type Output Type RA0 TTL CMOS AN0 AN — Description PORTA I/O with prog.
PIC16F610/616/16HV610/616 2.0 MEMORY ORGANIZATION 2.1 Program Memory Organization The PIC16F610/616/16HV610/616 has a 13-bit program counter capable of addressing an 8K x 14 program memory space. Only the first 1K x 14 (0000h-3FF) for the PIC16F610/16HV610 and the first 2K x 14 (0000h-07FFh) for the PIC16F616/16HV616 is physically implemented. Accessing a location above these boundaries will cause a wraparound within the first 1K x 14 space (PIC16F610/16HV610) and 2K x 14 space (PIC16F616/16HV616).
PIC16F610/616/16HV610/616 2.2 Data Memory Organization The data memory (see Figure 2-4) is partitioned into two banks, which contain the General Purpose Registers (GPR) and the Special Function Registers (SFR). The Special Function Registers are located in the first 32 locations of each bank. PIC16F610/16HV610 Register locations 40h-7Fh in Bank 0 are General Purpose Registers, implemented as static RAM.
PIC16F610/616/16HV610/616 FIGURE 2-3: DATA MEMORY MAP OF THE PIC16F610/16HV610 File Address FIGURE 2-4: File Address DATA MEMORY MAP OF THE PIC16F616/16HV616 File Address File Address Indirect Addr.(1) 00h Indirect Addr.(1) 80h Indirect Addr.(1) 00h Indirect Addr.
PIC16F610/616/16HV610/616 TABLE 2-1: Addr Name PIC16F610/616/16HV610/616 SPECIAL FUNCTION REGISTERS SUMMARY BANK 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Page Bank 0 00h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 24, 116 01h TMR0 Timer0 Module’s Register xxxx xxxx 45, 116 02h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 24, 116 03h STATUS 0001 1xxx 18, 116 04h FSR 05h
PIC16F610/616/16HV610/616 TABLE 2-2: Addr PIC16F610/616/16HV610/616 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1 Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Page Bank 1 80h INDF 81h OPTION_REG Addressing this location uses contents of FSR to address data memory (not a physical register) 82h PCL 83h STATUS FSR 85h TRISA 86h INTEDG T0CS T0SE IRP(1) RP1(1) RP0 PS2 PS1 PS0 1111 1111 19, 116 TO PD Z DC C 0001 1xxx 18, 116 0000 0000 24, 116 Indirec
PIC16F610/616/16HV610/616 2.2.2.1 STATUS Register The STATUS register, shown in Register 2-1, contains: • the arithmetic status of the ALU • the Reset status • the bank select bits for data memory (RAM) The STATUS register can be the destination for any instruction, like any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic.
PIC16F610/616/16HV610/616 2.2.2.2 OPTION Register Note: The OPTION register is a readable and writable register, which contains various control bits to configure: • • • • Timer0/WDT prescaler External RA2/INT interrupt Timer0 Weak pull-ups on PORTA REGISTER 2-2: To achieve a 1:1 prescaler assignment for Timer0, assign the prescaler to the WDT by setting PSA bit to ‘1’ of the OPTION register. See Section 5.1.3 “Software Programmable Prescaler”.
PIC16F610/616/16HV610/616 2.2.2.3 INTCON Register Note: The INTCON register is a readable and writable register, which contains the various enable and flag bits for TMR0 register overflow, PORTA change and external RA2/INT pin interrupts. REGISTER 2-3: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE of the INTCON register.
PIC16F610/616/16HV610/616 2.2.2.4 PIE1 Register The PIE1 register contains the peripheral interrupt enable bits, as shown in Register 2-4. REGISTER 2-4: Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt.
PIC16F610/616/16HV610/616 2.2.2.5 PIR1 Register The PIR1 register contains the peripheral interrupt flag bits, as shown in Register 2-5. REGISTER 2-5: Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
PIC16F610/616/16HV610/616 2.2.2.6 PCON Register The Power Control (PCON) register (see Table 12-2) contains flag bits to differentiate between a: • • • • Power-on Reset (POR) Brown-out Reset (BOR) Watchdog Timer Reset (WDT) External MCLR Reset The PCON register also controls the software enable of the BOR. The PCON register bits are shown in Register 2-6.
PIC16F610/616/16HV610/616 2.3 PCL and PCLATH 2.3.2 The Program Counter (PC) is 13 bits wide. The low byte comes from the PCL register, which is a readable and writable register. The high byte (PC<12:8>) is not directly readable or writable and comes from PCLATH. On any Reset, the PC is cleared. Figure 2-5 shows the two situations for the loading of the PC. The upper example in Figure 2-5 shows how the PC is loaded on a write to PCL (PCLATH<4:0> → PCH).
PIC16F610/616/16HV610/616 FIGURE 2-6: DIRECT/INDIRECT ADDRESSING PIC16F610/16HV610 Direct Addressing (1) RP1 RP0 6 Bank Select From Opcode Indirect Addressing IRP(1) 0 7 File Select Register Bank Select Location Select 00 01 10 0 Location Select 11 00h 180h NOT USED(2) Data Memory 1FFh 7Fh Bank 0 Bank 1 Bank 2 Bank 3 For memory map detail, see Figure 2-3. Unimplemented data memory locations, read as ‘0’.
PIC16F610/616/16HV610/616 NOTES: DS41288F-page 26 © 2009 Microchip Technology Inc.
PIC16F610/616/16HV610/616 3.0 OSCILLATOR MODULE The Oscillator module can be configured in one of eight clock modes. 3.1 Overview 1. 2. 3. The Oscillator module has a wide variety of clock sources and selection features that allow it to be used in a wide range of applications while maximizing performance and minimizing power consumption. Figure 3-1 illustrates a block diagram of the Oscillator module.
PIC16F610/616/16HV610/616 3.2 3.3.2 Clock Source Modes Clock Source modes can be classified as external or internal. • External Clock modes rely on external circuitry for the clock source. Examples are: Oscillator modules (EC mode), quartz crystal resonators or ceramic resonators (LP, XT and HS modes) and Resistor-Capacitor (RC) mode circuits. • Internal clock sources are contained internally within the Oscillator module.
PIC16F610/616/16HV610/616 3.3.3 LP, XT, HS MODES The LP, XT and HS modes support the use of quartz crystal resonators or ceramic resonators connected to OSC1 and OSC2 (Figure 3-3). The mode selects a low, medium or high gain setting of the internal inverteramplifier to support various resonator types and speed. LP Oscillator mode selects the lowest gain setting of the internal inverter-amplifier. LP mode current consumption is the least of the three modes. This mode is designed to drive only 32.
PIC16F610/616/16HV610/616 3.3.4 EXTERNAL RC MODES 3.4 The external Resistor-Capacitor (RC) modes support the use of an external RC circuit. This allows the designer maximum flexibility in frequency choice while keeping costs to a minimum when clock accuracy is not required. There are two modes: RC and RCIO. In RC mode, the RC circuit connects to OSC1. OSC2/ CLKOUT outputs the RC oscillator frequency divided by 4.
PIC16F610/616/16HV610/616 3.4.1.1 OSCTUNE Register The default value of the OSCTUNE register is ‘0’. The value is a 5-bit two’s complement number. The oscillator is factory calibrated but can be adjusted in software by writing to the OSCTUNE register (Register 3-1). REGISTER 3-1: When the OSCTUNE register is modified, the frequency will begin shifting to the new frequency. Code execution continues during this shift. There is no indication that the shift has occurred.
PIC16F610/616/16HV610/616 NOTES: DS41288F-page 32 © 2009 Microchip Technology Inc.
PIC16F610/616/16HV610/616 4.0 I/O PORTS port pins are read, this value is modified and then written to the PORT data latch. RA3 reads ‘0’ when MCLRE = 1. There are as many as eleven general purpose I/O pins and an input pin available. Depending on which peripherals are enabled, some or all of the pins may not be available as general purpose I/O. In general, when a peripheral is enabled, the associated pin may not be used as a general purpose I/O pin. 4.
PIC16F610/616/16HV610/616 4.2 4.2.3 Additional Pin Functions INTERRUPT-ON-CHANGE Every PORTA pin on the PIC16F610/616/16HV610/ 616 has an interrupt-on-change option and a weak pullup option. The next three sections describe these functions. Each PORTA pin is individually configurable as an interrupt-on-change pin. Control bits IOCAx enable or disable the interrupt function for each pin. Refer to Register 4-5. The interrupt-on-change is disabled on a Power-on Reset. 4.2.
PIC16F610/616/16HV610/616 REGISTER 4-4: WPUA: WEAK PULL-UP PORTA REGISTER U-0 U-0 R/W-1 R/W-1 U-0 R/W-1 R/W-1 R/W-1 — — WPUA5 WPUA4 — WPUA2 WPUA1 WPUA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 WPUA<5:4>: Weak Pull-up Control bits 1 = Pull-up enabled 0 = Pull-up disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 WPUA<2:0>: Weak Pull
PIC16F610/616/16HV610/616 4.2.4 PIN DESCRIPTIONS AND DIAGRAMS Each PORTA pin is multiplexed with other functions. The pins and their combined functions are briefly described here. For specific information about individual functions such as the Comparator or the ADC, refer to the appropriate section in this data sheet. RA0/AN0(1)/C1IN+/ICSPDAT 4.2.4.1 Figure 4-1 shows the diagram for this pin.
PIC16F610/616/16HV610/616 RA2/AN2(1)/T0CKI/INT/C1OUT 4.2.4.3 Figure 4-2 shows the diagram for this pin. The RA2 pin is configurable to function as one of the following: • • • • • a general purpose I/O an analog input for the ADC(1) the clock input for TMR0 an external edge triggered interrupt a digital output from Comparator C1 Note 1: PIC16F616/16HV616 only.
PIC16F610/616/16HV610/616 4.2.4.4 RA3/MCLR/VPP Figure 4-3 shows the diagram for this pin.
PIC16F610/616/16HV610/616 4.2.4.5 RA4/AN3(1)/T1G/OSC2/CLKOUT • a Timer1 gate (count enable) • a crystal/resonator connection • a clock output Figure 4-4 shows the diagram for this pin. The RA4 pin is configurable to function as one of the following: Note 1: PIC16F616/16HV616 only.
PIC16F610/616/16HV610/616 4.2.4.6 RA5/T1CKI/OSC1/CLKIN • • • • Figure 4-5 shows the diagram for this pin.
PIC16F610/616/16HV610/616 TABLE 4-1: Name SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Bit 0 Value on POR, BOR Value on all other Resets ANS1 ANS0 1111 1111 1111 1111 C1CH1 C1CH0 0000 -000 0000 -000 C2CH0 0000 -000 0000 -000 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 ANSEL ANS7 ANS6 ANS5 ANS4 ANS3(1) ANS2(1) CM1CON0 C1ON C1OUT C1OE C1POL — C1R CM2CON0 C2ON C2OUT C2OE C2POL — C2R C2CH1 GIE PEIE T0IE INTE RAIE T0IF INTF RAIF 0000 0000 0000 0000 — — IOCA5 IOCA4 I
PIC16F610/616/16HV610/616 4.3 PORTC and the TRISC Registers PORTC is a general purpose I/O port consisting of 6 bidirectional pins. The pins can be configured for either digital I/O or analog input to A/D Converter (ADC) or Comparator. For specific information about individual functions such as the Enhanced CCP or the ADC, refer to the appropriate section in this data sheet. Note: The ANSEL register must be initialized to configure an analog channel as a digital input.
PIC16F610/616/16HV610/616 RC0/AN4(1)/C2IN+ 4.3.1 RC2/AN6(1)/C12IN2-/P1D(1) 4.3.3 The RC0 is configurable to function as one of the following: The RC2 is configurable to function as one of the following: • a general purpose I/O • an analog input for the ADC(1) • an analog non-inverting input to Comparator C2 • • • • RC1/AN5(1)/C12IN1- 4.3.
PIC16F610/616/16HV610/616 RC4/C2OUT/P1B(1) 4.3.5 RC5/CCP1(1)/P1A(1) 4.3.6 The RC4 is configurable to function as one of the following: The RC5 is configurable to function as one of the following: • a general purpose I/O • a digital output from Comparator C2 • a digital output from the Enhanced CCP(1) • a general purpose I/O • a digital input/output for the Enhanced CCP(1) Note 1: PIC16F616/16HV616 only. Note 1: PIC16F616/16HV616 only.
PIC16F610/616/16HV610/616 5.0 TIMER0 MODULE 5.1 Timer0 Operation The Timer0 module is an 8-bit timer/counter with the following features: When used as a timer, the Timer0 module can be used as either an 8-bit timer or an 8-bit counter. • • • • • 5.1.
PIC16F610/616/16HV610/616 5.1.3 SOFTWARE PROGRAMMABLE PRESCALER A single software programmable prescaler is available for use with either Timer0 or the Watchdog Timer (WDT), but not both simultaneously. The prescaler assignment is controlled by the PSA bit of the OPTION register. To assign the prescaler to Timer0, the PSA bit must be cleared to a ‘0’. There are 8 prescaler options for the Timer0 module ranging from 1:2 to 1:256.
PIC16F610/616/16HV610/616 REGISTER 5-1: OPTION_REG: OPTION REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 RAPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 RAPU: PORTA Pull-up Enable bit 1 = PORTA pull-ups are disabled 0 = PORTA pull-ups are enabled by individual PORT latch values bit 6 INTEDG: Interrupt Edge Select bit 1 = Interrup
PIC16F610/616/16HV610/616 NOTES: DS41288F-page 48 © 2009 Microchip Technology Inc.
PIC16F610/616/16HV610/616 6.0 TIMER1 MODULE WITH GATE CONTROL 6.1 The Timer1 module is a 16-bit incrementing counter which is accessed through the TMR1H:TMR1L register pair. Writes to TMR1H or TMR1L directly update the counter.
PIC16F610/616/16HV610/616 6.2.1 INTERNAL CLOCK SOURCE When the internal clock source is selected the TMR1H:TMR1L register pair will increment on multiples of TCY as determined by the Timer1 prescaler. 6.2.2 EXTERNAL CLOCK SOURCE When the external clock source is selected, the Timer1 module may work as a timer or a counter. When counting, Timer1 is incremented on the rising edge of the external clock input T1CKI.
PIC16F610/616/16HV610/616 other applications. For more information on Delta-Sigma A/D converters, see the Microchip web site (www.microchip.com). Note: TMR1GE bit of the T1CON register must be set to use either T1G or C2OUT as the Timer1 gate source. See the CM2CON1 register (Register 8-3) for more information on selecting the Timer1 gate source. Timer1 gate can be inverted using the T1GINV bit of the T1CON register, whether it originates from the T1G pin or Comparator C2 output.
PIC16F610/616/16HV610/616 FIGURE 6-2: TIMER1 INCREMENTING EDGE T1CKI = 1 when TMR1 Enabled T1CKI = 0 when TMR1 Enabled Note 1: Arrows indicate counter increments. 2: 6.12 In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock. Timer1 Control Register The Timer1 Control register (T1CON), shown in Register 6-1, is used to control Timer1 and select the various features of the Timer1 module.
PIC16F610/616/16HV610/616 REGISTER 6-1: T1CON: TIMER1 CONTROL REGISTER (CONTINUED) bit 2 T1SYNC: Timer1 External Clock Input Synchronization Control bit TMR1CS = 1: 1 = Do not synchronize external clock input 0 = Synchronize external clock input TMR1CS = 0: This bit is ignored.
PIC16F610/616/16HV610/616 TABLE 6-1: Name SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets 0000 -000 CM2CON0 C2ON C2OUT C2OE C2POL — C2R C2CH1 C2CH0 0000 -000 CM2CON1 MC1OUT MC2OUT — T1ACS C1HYS C2HYS T1GSS C2SYNC 00-0 0010 00-0 0010 GIE PEIE T0IE INTE RAIE T0IF INTF RAIF 0000 0000 0000 0000 PIE1 — ADIE(1) CCP1IE(1) C2IE C1IE — TMR2IE(1) TMR1IE -000 0-00 -000 0-00 PIR1
PIC16F610/616/16HV610/616 7.0 TIMER2 MODULE (PIC16F616/16HV616 ONLY) The TMR2 and PR2 registers are both fully readable and writable. On any Reset, the TMR2 register is set to 00h and the PR2 register is set to FFh.
PIC16F610/616/16HV610/616 REGISTER 7-1: T2CON: TIMER2 CONTROL REGISTER U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’ bit 6-3 TOUTPS<3:0>: Timer2 Output Postscaler Select bits 0000 = 1:1 Postscaler 0001 = 1:2 Postscaler 0010 = 1:3 Postscaler 0011 =
PIC16F610/616/16HV610/616 8.0 COMPARATOR MODULE Comparators are used to interface analog circuits to a digital circuit by comparing two analog voltages and providing a digital indication of their relative magnitudes. The comparators are very useful mixed signal building blocks because they provide analog functionality independent of the device.
PIC16F610/616/16HV610/616 FIGURE 8-2: COMPARATOR C1 SIMPLIFIED BLOCK DIAGRAM C1CH<1:0> C1POL 2 D C12IN0- 0 C12IN1C12IN2- 1 MUX 2 C12IN3- 3 Q1 To Data Bus Q EN RD_CM1CON0 Set C1IF D Q3*RD_CM1CON0 Q EN CL To PWM Logic Reset C1ON(1) C1R C1IN+ C1OE 0 MUX 1 C1VREF C1VIN- C1VIN+ C1 + C1OUT C1OUT pin(2) C1POL Note 1: 2: FIGURE 8-3: When C1ON = 0, the C1 comparator will produce a ‘0’ output to the XOR Gate. Output shown for reference only. See I/O port pin block diagram for more detail.
PIC16F610/616/16HV610/616 8.2 Comparator Control Each comparator has a separate control and Configuration register: CM1CON0 for Comparator C1 and CM2CON0 for Comparator C2. In addition, Comparator C2 has a second control register, CM2CON1, for controlling the interaction with Timer1 and simultaneous reading of both comparator outputs.
PIC16F610/616/16HV610/616 8.4 Comparator Interrupt Operation The comparator interrupt flag can be set whenever there is a change in the output value of the comparator. Changes are recognized by means of a mismatch circuit which consists of two latches and an exclusive-or gate (see Figure 8-2 and Figure 8-3). One latch is updated with the comparator output level when the CMxCON0 register is read. This latch retains the value until the next read of the CMxCON0 register or the occurrence of a Reset.
PIC16F610/616/16HV610/616 8.5 Operation During Sleep The comparator, if enabled before entering Sleep mode, remains active during Sleep. The additional current consumed by the comparator is shown separately in Section 15.0 “Electrical Specifications”. If the comparator is not used to wake the device, power consumption can be minimized while in Sleep mode by turning off the comparator. Each comparator is turned off by clearing the CxON bit of the CMxCON0 register.
PIC16F610/616/16HV610/616 REGISTER 8-1: CM1CON0: COMPARATOR 1 CONTROL REGISTER 0 R/W-0 R-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 C1ON C1OUT C1OE C1POL — C1R C1CH1 C1CH0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 C1ON: Comparator C1 Enable bit 1 = Comparator C1 is enabled 0 = Comparator C1 is disabled bit 6 C1OUT: Comparator C1 Output bit If C1POL = 1 (inverted polarity): C1OUT
PIC16F610/616/16HV610/616 REGISTER 8-2: CM2CON0: COMPARATOR 2 CONTROL REGISTER 0 R/W-0 R-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 C2ON C2OUT C2OE C2POL — C2R C2CH1 C2CH0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 C2ON: Comparator C2 Enable bit 1 = Comparator C2 is enabled 0 = Comparator C2 is disabled bit 6 C2OUT: Comparator C2 Output bit If C2POL = 1 (inverted polarity): C2OUT
PIC16F610/616/16HV610/616 8.7 Comparator Analog Input Connection Considerations A simplified circuit for an analog input is shown in Figure 8-6. Since the analog input pins share their connection with a digital input, they have reverse biased ESD protection diodes to VDD and VSS. The analog input, therefore, must be between VSS and VDD. If the input voltage deviates from this range by more than 0.6V in either direction, one of the diodes is forward biased and a latch-up may occur.
PIC16F610/616/16HV610/616 8.8 8.8.2 Additional Comparator Features There are three additional comparator features: The Comparator C2 output can be synchronized with Timer1 by setting the C2SYNC bit of the CM2CON1 register. When enabled, the C2 output is latched on the falling edge of the Timer1 clock source. If a prescaler is used with Timer1, the comparator output is latched after the prescaling function.
PIC16F610/616/16HV610/616 8.9 Comparator Hysteresis Each comparator has built-in hysteresis that is user enabled by setting the C1HYS or C2HYS bits of the CM2CON1 register. The hysteresis feature can help filter noise and reduce multiple comparator output transitions when the output is changing state. FIGURE 8-7: Figure 8-9 shows the relationship between the analog input levels and digital output of a comparator with and without hysteresis.
PIC16F610/616/16HV610/616 TABLE 8-2: Name SUMMARY OF REGISTERS ASSOCIATED WITH THE COMPARATOR AND VOLTAGE REFERENCE MODULES Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets ANSEL ANS7 ANS6 ANS5 ANS4 ANS3(1) ANS2(1) ANS1 ANS0 1111 1111 1111 1111 CM1CON0 C1ON C1OUT C1OE C1POL C1SP C1R C1CH1 C1CH0 0000 0000 0000 0000 CM2CON0 C2ON C2OUT C2OE C2POL C2SP C2R C2CH1 C2CH0 0000 0000 0000 0000 CM2CON1 MC1OUT MC2OUT — T1ACS C1
PIC16F610/616/16HV610/616 8.10 Comparator SR Latch inputs are high the latch will go to the Reset state. Both the PULSS and PULSR bits are self resetting which means that a single write to either of the bits is all that is necessary to complete a latch Set or Reset operation. The SR latch module provides additional control of the comparator outputs. The module consists of a single SR latch and output multiplexers. The SR latch can be set, reset or toggled by the comparator outputs.
PIC16F610/616/16HV610/616 REGISTER 8-4: SRCON0: SR LATCH CONTROL 0 REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/S-0 R/S-0 U-0 R/W-0 SR1(2) SR0(2) C1SEN C2REN PULSS PULSR — SRCLKEN bit 7 bit 0 Legend: S = Bit is set only - R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SR1: SR Latch Configuration bit(2) 1= C2OUT pin is the latch Q output 0= C2OUT pin is the C2 comparator output bit 6 S
PIC16F610/616/16HV610/616 8.11 Comparator Voltage Reference The comparator voltage reference module provides an internally generated voltage reference for the comparators. The following features are available: • • • • • Independent from Comparator operation Two 16-level voltage ranges Output clamped to VSS Ratiometric with VDD Fixed Reference (0.6V) The VRCON register (Register 8-6) controls the voltage reference module shown in Figure 8-9. 8.11.1 8.11.
PIC16F610/616/16HV610/616 8.11.5 FIXED VOLTAGE REFERENCE 8.11.7 The fixed voltage reference is independent of VDD, with a nominal output voltage of 0.6V. This reference can be enabled by setting the FVREN bit of the VRCON register to ‘1’. This reference is always enabled when the HFINTOSC oscillator is active. 8.11.6 Multiplexers on the output of the voltage reference module enable selection of either the CVREF or fixed voltage reference for use by the comparators.
PIC16F610/616/16HV610/616 REGISTER 8-6: VRCON: VOLTAGE REFERENCE CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 C1VREN C2VREN VRR FVREN VR3 VR2 VR1 VR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 C1VREN: Comparator 1 Voltage Reference Enable bit 1 = CVREF circuit powered on and routed to C1VREF input of Comparator C1 0 = 0.
PIC16F610/616/16HV610/616 9.0 ANALOG-TO-DIGITAL CONVERTER (ADC) MODULE (PIC16F616/16HV616 ONLY) Note: The ADRESL and ADRESH registers are read-only. The Analog-to-Digital Converter (ADC) allows conversion of an analog input signal to a 10-bit binary representation of that signal. This device uses analog inputs, which are multiplexed into a single sample and hold circuit. The output of the sample and hold is connected to the input of the converter.
PIC16F610/616/16HV610/616 9.1 9.1.4 ADC Configuration The source of the conversion clock is software selectable via the ADCS bits of the ADCON1 register. There are seven possible clock options: When configuring and using the ADC, the following functions must be considered: • • • • • • Port configuration Channel selection ADC voltage reference selection ADC conversion clock source Interrupt control Results formatting 9.1.
PIC16F610/616/16HV610/616 FIGURE 9-2: ANALOG-TO-DIGITAL CONVERSION TAD CYCLES TCY to TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Conversion Starts Holding Capacitor is Disconnected from Analog Input (typically 100 ns) Set GO/DONE bit 9.1.5 ADRESH and ADRESL registers are loaded, GO bit is cleared, ADIF bit is set, Holding capacitor is connected to analog input INTERRUPTS 9.1.
PIC16F610/616/16HV610/616 9.2 9.2.1 ADC Operation STARTING A CONVERSION To enable the ADC module, the ADON bit of the ADCON0 register must be set to a ‘1’. Setting the GO/ DONE bit of the ADCON0 register to a ‘1’ will start the analog-to-digital conversion. Note: 9.2.2 The GO/DONE bit should not be set in the same instruction that turns on the ADC. Refer to Section 9.2.6 “A/D Conversion Procedure”. COMPLETION OF A CONVERSION 9.2.
PIC16F610/616/16HV610/616 EXAMPLE 9-1: A/D CONVERSION ;This code block configures the ADC ;for polling, Vdd reference, Frc clock ;and AN0 input. ; ;Conversion start & polling for completion ; are included.
PIC16F610/616/16HV610/616 9.2.7 ADC REGISTER DEFINITIONS The following registers are used to control the operation of the ADC.
PIC16F610/616/16HV610/616 REGISTER 9-2: ADCON1: A/D CONTROL REGISTER 1 U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — ADCS2 ADCS1 ADCS0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’ bit 6-4 ADCS<2:0>: A/D Conversion Clock Select bits 000 = FOSC/2 001 = FOSC/8 010 = FOSC/32 x11 = FRC (clock derived from a dedicated internal oscillator = 500 kHz max)
PIC16F610/616/16HV610/616 REGISTER 9-3: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 0 (READ-ONLY) R-x R-x R-x R-x R-x R-x R-x R-x ADRES9 ADRES8 ADRES7 ADRES6 ADRES5 ADRES4 ADRES3 ADRES2 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 x = Bit is unknown ADRES<9:2>: ADC Result Register bits Upper 8 bits of 10-bit conversion result REGISTER 9-4: ADRESL: ADC RESULT REGISTER
PIC16F610/616/16HV610/616 9.3 A/D Acquisition Requirements For the ADC to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The Analog Input model is shown in Figure 9-4. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD), see Figure 9-4.
PIC16F610/616/16HV610/616 FIGURE 9-4: ANALOG INPUT MODEL VDD ANx Rs CPIN 5 pF VA VT = 0.6V VT = 0.
PIC16F610/616/16HV610/616 TABLE 9-2: Name ADCON0(1) ADCON1 (1) ANSEL SUMMARY OF ASSOCIATED ADC REGISTERS Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets ADFM VCFG CHS3 CHS2 CHS1 CHS0 GO/DONE ADON 0000 0000 0000 0000 — ADCS2 ADCS1 ADCS0 — — — — -000 ---- -000 ---- ANS ANS6 ANS5 ANS4 ANS3(1) ANS2(1) ANS1 ANS0 1111 1111 1111 1111 uuuu uuuu ADRESH(1,2) A/D Result Register High Byte xxxx xxxx ADRESL(1,2) A/D Result Registe
PIC16F610/616/16HV610/616 NOTES: DS41288F-page 84 © 2009 Microchip Technology Inc.
PIC16F610/616/16HV610/616 10.0 ENHANCED CAPTURE/ COMPARE/PWM (WITH AUTOSHUTDOWN AND DEAD BAND) MODULE (PIC16F616/16HV616 ONLY) The Enhanced Capture/Compare/PWM module is a peripheral which allows the user to time and control different events. In Capture mode, the peripheral allows the timing of the duration of an event. The Compare mode allows the user to trigger an external REGISTER 10-1: event when a predetermined amount of time has expired.
PIC16F610/616/16HV610/616 10.1 10.1.2 Capture Mode In Capture mode, CCPR1H:CCPR1L captures the 16-bit value of the TMR1 register when an event occurs on pin CCP1. An event is defined as one of the following and is configured by the CCP1M<3:0> bits of the CCP1CON register: • • • • Every falling edge Every rising edge Every 4th rising edge Every 16th rising edge When a capture is made, the Interrupt Request Flag bit CCP1IF of the PIR1 register is set. The interrupt flag must be cleared in software.
PIC16F610/616/16HV610/616 TABLE 10-2: Name CCP1CON(1) SUMMARY OF REGISTERS ASSOCIATED WITH CAPTURE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 CCPR1L(1) Capture/Compare/PWM Register 1 Low Byte CCPR1H(1) Capture/Compare/PWM Register 1 High Byte Value on POR, BOR Value on all other Resets 0000 0000 0000 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu GIE PEIE T0IE INTE RAIE T0IF INTF RAIF 0000 0000 0000 0000 PIE1 — ADI
PIC16F610/616/16HV610/616 10.2 10.2.2 Compare Mode In Compare mode, the 16-bit CCPR1 register value is constantly compared against the TMR1 register pair value. When a match occurs, the CCP1 module may: • • • • • Toggle the CCP1 output Set the CCP1 output Clear the CCP1 output Generate a Special Event Trigger Generate a Software Interrupt All Compare modes can generate an interrupt.
PIC16F610/616/16HV610/616 TABLE 10-3: Name CCP1CON(1) SUMMARY OF REGISTERS ASSOCIATED WITH COMPARE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 CCPR1L(1) Capture/Compare/PWM Register 1 Low Byte CCPR1H(1) Capture/Compare/PWM Register 1 High Byte Value on POR, BOR Value on all other Resets 0000 0000 0000 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu GIE PEIE T0IE INTE RAIE T0IF INTF RAIF 0000 0000 0000 0000 PIE1 — ADI
PIC16F610/616/16HV610/616 10.3 PWM Mode The PWM mode generates a Pulse-Width Modulated signal on the CCP1 pin. The duty cycle, period and resolution are determined by the following registers: • • • • PR2 T2CON CCPR1L CCP1CON FIGURE 10-4: CCP PWM OUTPUT Period Pulse Width In Pulse-Width Modulation (PWM) mode, the CCP module produces up to a 10-bit resolution PWM output on the CCP1 pin.
PIC16F610/616/16HV610/616 10.3.1 PWM PERIOD EQUATION 10-2: The PWM period is specified by writing to the PR2 register of Timer2. The PWM period can be calculated using the formula of Equation 10-1.
PIC16F610/616/16HV610/616 10.3.4 OPERATION IN SLEEP MODE In Sleep mode, the TMR2 register will not increment and the state of the module will not change. If the CCP1 pin is driving a value, it will continue to drive that value. When the device wakes up, TMR2 will continue from its previous state. 10.3.5 CHANGES IN SYSTEM CLOCK FREQUENCY The PWM frequency is derived from the system clock frequency. Any changes in the system clock frequency will result in changes to the PWM frequency. See Section 3.
PIC16F610/616/16HV610/616 10.4 PWM (Enhanced Mode) The PWM outputs are multiplexed with I/O pins and are designated P1A, P1B, P1C and P1D. The polarity of the PWM pins is configurable and is selected by setting the CCP1M bits in the CCP1CON register appropriately. The Enhanced PWM Mode can generate a PWM signal on up to four different output pins with up to 10-bits of resolution.
PIC16F610/616/16HV610/616 FIGURE 10-6: EXAMPLE PWM (ENHANCED MODE) OUTPUT RELATIONSHIPS (ACTIVE-HIGH STATE) P1M<1:0> Signal PR2+1 Pulse Width 0 Period 00 (Single Output) P1A Modulated Delay(1) Delay(1) P1A Modulated 10 (Half-Bridge) P1B Modulated P1A Active 01 (Full-Bridge, Forward) P1B Inactive P1C Inactive P1D Modulated P1A Inactive 11 (Full-Bridge, Reverse) P1B Modulated P1C Active P1D Inactive Relationships: • Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value) • Pulse Width = TOSC
PIC16F610/616/16HV610/616 FIGURE 10-7: EXAMPLE ENHANCED PWM OUTPUT RELATIONSHIPS (ACTIVE-LOW STATE) Signal P1M<1:0> PR2+1 Pulse Width 0 Period 00 (Single Output) P1A Modulated P1A Modulated Delay(1) 10 (Half-Bridge) Delay(1) P1B Modulated P1A Active 01 (Full-Bridge, Forward) P1B Inactive P1C Inactive P1D Modulated P1A Inactive 11 (Full-Bridge, Reverse) P1B Modulated P1C Active P1D Inactive Relationships: • Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value) • Pulse Width = TOSC * (CCPR1
PIC16F610/616/16HV610/616 10.4.1 HALF-BRIDGE MODE In Half-Bridge mode, two pins are used as outputs to drive push-pull loads. The PWM output signal is output on the CCP1/P1A pin, while the complementary PWM output signal is output on the P1B pin (see Figure 10-8). This mode can be used for half-bridge applications, as shown in Figure 10-9, or for full-bridge applications, where four power switches are being modulated with two PWM signals.
PIC16F610/616/16HV610/616 10.4.2 FULL-BRIDGE MODE P1A, P1B, P1C and P1D outputs are multiplexed with the PORT data latches. The associated TRIS bits must be cleared to configure the P1A, P1B, P1C and P1D pins as outputs. In Full-Bridge mode, all four pins are used as outputs. An example of full-bridge application is shown in Figure 10-10. In the Forward mode, pin CCP1/P1A is driven to its active state, pin P1D is modulated, while P1B and P1C will be driven to their inactive state as shown in Figure 1011.
PIC16F610/616/16HV610/616 FIGURE 10-11: EXAMPLE OF FULL-BRIDGE PWM OUTPUT Forward Mode Period P1A (2) Pulse Width P1B(2) P1C(2) P1D(2) (1) (1) Reverse Mode Period Pulse Width P1A(2) P1B(2) P1C(2) P1D(2) (1) Note 1: 2: (1) At this time, the TMR2 register is equal to the PR2 register. Output signal is shown as active-high. DS41288F-page 98 © 2009 Microchip Technology Inc.
PIC16F610/616/16HV610/616 10.4.2.1 Direction Change in Full-Bridge Mode In the Full-Bridge mode, the P1M1 bit in the CCP1CON register allows users to control the forward/reverse direction. When the application firmware changes this direction control bit, the module will change to the new direction on the next PWM cycle. A direction change is initiated in software by changing the P1M1 bit of the CCP1CON register.
PIC16F610/616/16HV610/616 FIGURE 10-13: EXAMPLE OF PWM DIRECTION CHANGE AT NEAR 100% DUTY CYCLE Forward Period t1 Reverse Period P1A P1B DC P1C P1D PW TON External Switch C TOFF External Switch D Potential Shoot-Through Current Note 1: T = TOFF – TON All signals are shown as active-high. 2: TON is the turn on delay of power switch QC and its driver. 3: TOFF is the turn off delay of power switch QD and its driver. DS41288F-page 100 © 2009 Microchip Technology Inc.
PIC16F610/616/16HV610/616 10.4.3 START-UP CONSIDERATIONS When any PWM mode is used, the application hardware must use the proper external pull-up and/or pull-down resistors on the PWM output pins. Note: When the microcontroller is released from Reset, all of the I/O pins are in the highimpedance state. The external circuits must keep the power switch devices in the OFF state until the microcontroller drives the I/O pins with the proper signal levels or activates the PWM output(s).
PIC16F610/616/16HV610/616 10.4.4 ENHANCED PWM AUTOSHUTDOWN MODE The PWM mode supports an Auto-Shutdown mode that will disable the PWM outputs when an external shutdown event occurs. Auto-Shutdown mode places the PWM output pins into a predetermined state. This mode is used to help prevent the PWM from damaging the application. The auto-shutdown sources are selected using the ECCPASx bits of the ECCPAS register.
PIC16F610/616/16HV610/616 Note 1: The auto-shutdown condition is a levelbased signal, not an edge-based signal. As long as the level is present, the autoshutdown will persist. 2: Writing to the ECCPASE bit is disabled while an auto-shutdown condition persists. 3: Once the auto-shutdown condition has been removed and the PWM restarted (either through firmware or auto-restart), the PWM signal will always restart at the beginning of the next PWM period.
PIC16F610/616/16HV610/616 10.4.6 PROGRAMMABLE DEAD-BAND DELAY MODE FIGURE 10-16: In half-bridge applications where all power switches are modulated at the PWM frequency, the power switches normally require more time to turn off than to turn on. If both the upper and lower power switches are switched at the same time (one turned on, and the other turned off), both switches may be on for a short period of time until one switch completely turns off.
PIC16F610/616/16HV610/616 REGISTER 10-3: PWM1CON: ENHANCED PWM CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PRSEN PDC6 PDC5 PDC4 PDC3 PDC2 PDC1 PDC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 PRSEN: PWM Restart Enable bit 1 = Upon auto-shutdown, the ECCPASE bit clears automatically once the shutdown event goes away; the PWM restarts au
PIC16F610/616/16HV610/616 NOTES: DS41288F-page 106 © 2009 Microchip Technology Inc.
PIC16F610/616/16HV610/616 11.0 VOLTAGE REGULATOR The PIC16HV610/16HV616 include a permanent internal 5 volt (nominal) shunt regulator in parallel with the VDD pin. This eliminates the need for an external voltage regulator in systems sourced by an unregulated supply. All external devices connected directly to the VDD pin will share the regulated supply voltage and contribute to the total VDD supply current (ILOAD). 11.
PIC16F610/616/16HV610/616 NOTES: DS41288F-page 108 © 2009 Microchip Technology Inc.
PIC16F610/616/16HV610/616 12.0 SPECIAL FEATURES OF THE CPU The PIC16F610/616/16HV610/616 has a host of features intended to maximize system reliability, minimize cost through elimination of external components, provide power-saving features and offer code protection.
PIC16F610/616/16HV610/616 REGISTER 12-1: — CONFIG: CONFIGURATION WORD REGISTER — — — — — BOREN1(1) BOREN0(1) bit 15 bit 8 CP(2) IOSCFS MCLRE(3) PWRTE WDTE FOSC2 FOSC1 FOSC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit P = Programmable’ U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-10 Unimplemented: Read as ‘1’ bit 9-8 BOREN<1:0>: Brown-out Reset Selection bits(1) 11 = BOR enabled 10 = BOR enabled d
PIC16F610/616/16HV610/616 12.2 Calibration Bits The 8 MHz internal oscillator is factory calibrated. These calibration values are stored in fuses located in the Calibration Word (2008h). The Calibration Word is not erased when using the specified bulk erase sequence in the Memory Programming Specification (DS41284) and thus, does not require reprogramming. 12.
PIC16F610/616/16HV610/616 12.3.1 POWER-ON RESET (POR) The on-chip POR circuit holds the chip in Reset until VDD has reached a high enough level for proper operation. To take advantage of the POR, simply connect the MCLR pin through a resistor to VDD. This will eliminate external RC components usually needed to create Power-on Reset. A maximum rise time for VDD is required. See Section 15.0 “Electrical Specifications” for details. If the BOR is enabled, the maximum rise time specification does not apply.
PIC16F610/616/16HV610/616 12.3.4 BROWN-OUT RESET (BOR) On any Reset (Power-on, Brown-out Reset, Watchdog timer, etc.), the chip will remain in Reset until VDD rises above VBOR (see Figure 12-3). If enabled, the Powerup Timer will be invoked by the Reset and keep the chip in Reset an additional 64 ms. The BOREN0 and BOREN1 bits in the Configuration Word register select one of three BOR modes. Selecting BOREN<1:0> = 10, the BOR is automatically disabled in Sleep to conserve power and enabled on wake-up.
PIC16F610/616/16HV610/616 12.3.5 TIME-OUT SEQUENCE 12.3.6 On power-up, the time-out sequence is as follows: The Power Control register PCON (address 8Eh) has two Status bits to indicate what type of Reset occurred last. • PWRT time-out is invoked after POR has expired. • OST is activated after the PWRT time-out has expired. Bit 0 is BOR (Brown-out). BOR is unknown on Poweron Reset.
PIC16F610/616/16HV610/616 FIGURE 12-4: TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR): CASE 1 VDD MCLR Internal POR TPWRT PWRT Time-out TOST OST Time-out Internal Reset TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR): CASE 2 FIGURE 12-5: VDD MCLR Internal POR TPWRT PWRT Time-out TOST OST Time-out Internal Reset FIGURE 12-6: TIME-OUT SEQUENCE ON POWER-UP (MCLR WITH VDD) VDD MCLR Internal POR TPWRT PWRT Time-out TOST OST Time-out Internal Reset © 2009 Microchip Technology Inc.
PIC16F610/616/16HV610/616 TABLE 12-4: Register INITIALIZATION CONDITION FOR REGISTERS Address Power-on Reset MCLR Reset WDT Reset Brown-out Reset(1) Wake-up from Sleep through Interrupt Wake-up from Sleep through WDT Time-out W INDF TMR0 — xxxx xxxx uuuu uuuu uuuu uuuu 00h/80h xxxx xxxx xxxx xxxx uuuu uuuu 01h xxxx xxxx uuuu uuuu uuuu uuuu PCL 02h/82h 0000 0000 0000 0000 PC + 1(3) STATUS 03h/83h 0001 1xxx 000q quuu(4) uuuq quuu(4) FSR 04h/84h xxxx xxxx uuuu uuuu uuuu uuuu
PIC16F610/616/16HV610/616 TABLE 12-4: INITIALIZATION CONDITION FOR REGISTERS (CONTINUED) Register Address Power-on Reset MCLR Reset WDT Reset (Continued) Brown-out Reset(1) Wake-up from Sleep through Interrupt Wake-up from Sleep through WDT Time-out (Continued) OSCTUNE 90h ---0 0000 ---u uuuu ---u uuuu ANSEL(7) 91h 1111 1111 1111 1111 uuuu uuuu PR2(6) 92h 1111 1111 1111 1111 1111 1111 WPUA 95h --11 -111 --11 -111 --uu -uuu IOCA 96h --00 0000 --00 0000 --uu uuuu SRCON0 99h 0
PIC16F610/616/16HV610/616 12.
PIC16F610/616/16HV610/616 12.4.2 TIMER0 INTERRUPT 12.4.3 An overflow (FFh → 00h) in the TMR0 register will set the T0IF bit of the INTCON register. The interrupt can be enabled/disabled by setting/clearing T0IE bit of the INTCON register. See Section 5.0 “Timer0 Module” for operation of the Timer0 module. An input change on PORTA sets the RAIF bit of the INTCON register. The interrupt can be enabled/ disabled by setting/clearing the RAIE bit of the INTCON register.
PIC16F610/616/16HV610/616 FIGURE 12-8: INT PIN INTERRUPT TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 CLKOUT (3) (4) INT pin (1) (1) INTF flag (INTCON reg.) Interrupt Latency (2) (5) GIE bit (INTCON reg.) INSTRUCTION FLOW PC Instruction Fetched INTCON Dummy Cycle Inst (PC) 0005h Inst (0004h) Inst (0005h) Dummy Cycle Inst (0004h) INTF flag is sampled here (every Q1). 2: Asynchronous interrupt latency = 3-4 TCY.
PIC16F610/616/16HV610/616 12.5 Context Saving During Interrupts During an interrupt, only the return PC value is saved on the stack. Typically, users may wish to save key registers during an interrupt (e.g., W and STATUS registers). This must be implemented in software. Temporary holding registers W_TEMP and STATUS_TEMP should be placed in the last 16 bytes of GPR (see Figure 2-4). These 16 locations are common to all banks and do not require banking.
PIC16F610/616/16HV610/616 12.6 12.6.1 Watchdog Timer (WDT) WDT PERIOD The WDT has a nominal time-out period of 18 ms (with no prescaler). The time-out periods vary with temperature, VDD and process variations from part to part (see Table 15-4, Parameter 31). If longer time-out periods are desired, a prescaler with a division ratio of up to 1:128 can be assigned to the WDT under software control by writing to the OPTION register. Thus, time-out periods up to 2.3 seconds can be realized.
PIC16F610/616/16HV610/616 TABLE 12-8: SUMMARY OF REGISTERS ASSOCIATED WITH WATCHDOG TIMER Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets OPTION_REG RAPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 IOSCFS CP MCLRE PWRTE WDTE FOSC2 FOSC1 FOSC0 — — (1) CONFIG Legend: Note 1: Shaded cells are not used by the Watchdog Timer. See Register 12-1 for operation of all Configuration Word register bits.
PIC16F610/616/16HV610/616 12.7 Power-Down Mode (Sleep) The Power-Down mode is entered by executing a SLEEP instruction. If the Watchdog Timer is enabled: • • • • • WDT will be cleared but keeps running. PD bit in the STATUS register is cleared. TO bit is set. Oscillator driver is turned off. I/O ports maintain the status they had before SLEEP was executed (driving high, low or high-impedance).
PIC16F610/616/16HV610/616 FIGURE 12-9: WAKE-UP FROM SLEEP THROUGH INTERRUPT Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 TOST(2) CLKOUT(4) INT pin INTF flag (INTCON reg.) Interrupt Latency (3) GIE bit (INTCON reg.) Instruction Flow PC Instruction Fetched Instruction Executed Note 12.
PIC16F610/616/16HV610/616 12.10 In-Circuit Serial Programming™ The PIC16F610/616/16HV610/616 microcontrollers can be serially programmed while in the end application circuit. This is simply done with five connections for: • • • • • clock data power ground programming voltage The device is placed into a Program/Verify mode by holding the RA0 and RA1 pins low, while raising the MCLR (VPP) pin from VIL to VIHH. See the Memory Programming Specification (DS41284) for more information.
PIC16F610/616/16HV610/616 FIGURE 12-11: 28 PIN ICD PINOUT 28-Pin PDIP In-Circuit Debug Device 1 2 3 28 27 26 4 5 25 24 6 7 8 9 10 11 PIC16F616-ICD VDD CS0 CS1 CS2 RA5 RA4 RA3 RC5 RC4 RC3 NC ICDCLK ICDMCLR ICDDATA 23 22 21 20 19 18 12 17 13 14 16 15 © 2009 Microchip Technology Inc.
PIC16F610/616/16HV610/616 NOTES: DS41288F-page 128 © 2009 Microchip Technology Inc.
PIC16F610/616/16HV610/616 13.
PIC16F610/616/16HV610/616 TABLE 13-2: PIC16F610/616/16HV610/616 INSTRUCTION SET Mnemonic, Operands 14-Bit Opcode Description Cycles MSb LSb Status Affected Notes BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF f, d f, d f – f, d f, d f, d f, d f, d f, d f, d f – f, d f, d f, d f, d f, d Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f, Skip if 0 Increment f Increment f, Skip if 0 I
PIC16F610/616/16HV610/616 13.2 Instruction Descriptions ADDLW Add literal and W Syntax: [ label ] ADDLW Operands: 0 ≤ k ≤ 255 Operation: (W) + k → (W) Status Affected: C, DC, Z Description: The contents of the W register are added to the eight-bit literal ‘k’ and the result is placed in the W register. k BCF Bit Clear f Syntax: [ label ] BCF Operands: 0 ≤ f ≤ 127 0≤b≤7 Operation: 0 → (f) Status Affected: None Description: Bit ‘b’ in register ‘f’ is cleared.
PIC16F610/616/16HV610/616 BTFSS Bit Test f, Skip if Set CLRWDT Clear Watchdog Timer Syntax: [ label ] BTFSS f,b Syntax: [ label ] CLRWDT Operands: 0 ≤ f ≤ 127 0≤b<7 Operands: None Operation: 00h → WDT 0 → WDT prescaler, 1 → TO 1 → PD Status Affected: TO, PD Description: CLRWDT instruction resets the Watchdog Timer. It also resets the prescaler of the WDT. Status bits TO and PD are set.
PIC16F610/616/16HV610/616 DECFSZ Decrement f, Skip if 0 INCFSZ Increment f, Skip if 0 Syntax: [ label ] DECFSZ f,d Syntax: [ label ] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (f) - 1 → (destination); skip if result = 0 Operation: (f) + 1 → (destination), skip if result = 0 Status Affected: None Status Affected: None Description: The contents of register ‘f’ are decremented. If ‘d’ is ‘0’, the result is placed in the W register.
PIC16F610/616/16HV610/616 MOVF Move f Syntax: [ label ] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] MOVF f,d MOVWF Move W to f Syntax: [ label ] MOVWF Operands: 0 ≤ f ≤ 127 Operation: (W) → (f) f Operation: (f) → (dest) Status Affected: None Status Affected: Z Description: Description: The contents of register ‘f’ is moved to a destination dependent upon the status of ‘d’. If d = 0, destination is W register. If d = 1, the destination is file register ‘f’ itself.
PIC16F610/616/16HV610/616 RETFIE Return from Interrupt RETLW Return with literal in W Syntax: [ label ] Syntax: [ label ] Operands: None Operands: 0 ≤ k ≤ 255 Operation: TOS → PC, 1 → GIE Operation: k → (W); TOS → PC Status Affected: None Status Affected: None Description: Return from Interrupt. Stack is POPed and Top-of-Stack (TOS) is loaded in the PC. Interrupts are enabled by setting Global Interrupt Enable bit, GIE (INTCON<7>). This is a two-cycle instruction.
PIC16F610/616/16HV610/616 RLF Rotate Left f through Carry SLEEP Enter Sleep mode Syntax: [ label ] Syntax: [ label ] SLEEP Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operands: None Operation: Operation: See description below Status Affected: C Description: The contents of register ‘f’ are rotated one bit to the left through the Carry flag. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’.
PIC16F610/616/16HV610/616 SUBWF Subtract W from f XORWF Exclusive OR W with f Syntax: [ label ] SUBWF f,d Syntax: [ label ] XORWF Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (f) - (W) → (destination) Operation: (W) .XOR. (F.) → (destination) Status Affected: C, DC, Z Status Affected: Z Description: Description: Exclusive OR the contents of the W register with register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register.
PIC16F610/616/16HV610/616 NOTES: DS41288F-page 138 © 2009 Microchip Technology Inc.
PIC16F610/616/16HV610/616 14.
PIC16F610/616/16HV610/616 14.2 MPLAB C Compilers for Various Device Families The MPLAB C Compiler code development systems are complete ANSI C compilers for Microchip’s PIC18, PIC24 and PIC32 families of microcontrollers and the dsPIC30 and dsPIC33 families of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger.
PIC16F610/616/16HV610/616 14.7 MPLAB SIM Software Simulator The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC® DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis.
PIC16F610/616/16HV610/616 14.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express 14.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits The PICkit™ 2 Development Programmer/Debugger is a low-cost development tool with an easy to use interface for programming and debugging Microchip’s Flash families of microcontrollers.
PIC16F610/616/16HV610/616 15.0 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings(†) Ambient temperature under bias..........................................................................................................-40° to +125°C Storage temperature ........................................................................................................................ -65°C to +150°C Voltage on VDD with respect to VSS ..................................................................................
PIC16F610/616/16HV610/616 FIGURE 15-1: PIC16F610/616 VOLTAGE-FREQUENCY GRAPH, -40°C ≤ TA ≤ +125°C 5.5 5.0 VDD (V) 4.5 4.0 3.5 3.0 2.5 2.0 0 8 10 20 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. FIGURE 15-2: PIC16HV610/616 VOLTAGE-FREQUENCY GRAPH, -40°C ≤ TA ≤ +125°C 5.0 VDD (V) 4.5 4.0 3.5 3.0 2.5 2.0 0 8 10 20 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
PIC16F610/616/16HV610/616 FIGURE 15-3: PIC16F610/616 FREQUENCY TOLERANCE GRAPH, -40°C ≤ TA ≤ +125°C 125 ± 5% Temperature (°C) 85 ± 2% 60 ± 1% 25 0 -40 2.5 2.0 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 15-4: PIC16HV610/616 FREQUENCY TOLERANCE GRAPH, -40°C ≤ TA ≤ +125°C 125 ± 5% Temperature (°C) 85 ± 2% 60 ± 1% 25 0 -40 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VDD (V) © 2009 Microchip Technology Inc.
PIC16F610/616/16HV610/616 15.1 DC Characteristics: PIC16F610/616/16HV610/616-I (Industrial) PIC16F610/616/16HV610/616-E (Extended) DC CHARACTERISTICS Param No. Sym VDD D001 Characteristic Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Min Typ† Max Units Conditions Supply Voltage PIC16F610/616 2.0 — 5.5 (2) V FOSC < = 4 MHz D001 PIC16HV610/616 2.
PIC16F610/616/16HV610/616 15.2 DC Characteristics: PIC16F610/616-I (Industrial) PIC16F610/616-E (Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended DC CHARACTERISTICS Param No. D010 Conditions Device Characteristics Min Typ† Max Units Note VDD Supply Current (IDD) PIC16F610/616 D011* D012 D013* D014 D016* D017 D018 D019 (1, 2) — 13 25 μA 2.0 — 19 29 μA 3.0 — 32 51 μA 5.
PIC16F610/616/16HV610/616 15.3 DC Characteristics: PIC16HV610/616-I (Industrial) PIC16HV610/616-E (Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended DC CHARACTERISTICS Param No. D010 Conditions Device Characteristics Min Typ† Max Units Note VDD Supply Current (IDD) PIC16HV610/616 D011* D012 D013* D014 D016* D017 D018 D019 (1, 2) — 160 230 μA 2.0 — 240 310 μA 3.
PIC16F610/616/16HV610/616 15.4 DC Characteristics: PIC16F610/616- I (Industrial) DC CHARACTERISTICS Param No. D020 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Conditions Device Characteristics Min Max Units VDD Note WDT, BOR, Comparators, VREF and T1OSC disabled 0.9 μA 2.0 0.15 1.2 μA 3.0 0.35 1.5 μA 5.0 150 500 nA 3.0 -40°C ≤ TA ≤ +25°C for industrial — 0.5 1.5 μA 2.0 WDT Current(1) — 2.5 4.0 μA 3.
PIC16F610/616/16HV610/616 15.5 DC Characteristics: PIC16F610/616-E (Extended) DC CHARACTERISTICS Param No. D020E Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +125°C for extended Conditions Device Characteristics Power-down Base Current (IPD)(2) PIC16F610/616 D021E Min — Typ† 0.05 Max 4.0 Units μA VDD Note 2.0 WDT, BOR, Comparators, VREF and T1OSC disabled — 0.15 5.0 μA 3.0 — 0.35 8.5 μA 5.0 — 0.5 5.0 μA 2.0 — 2.5 8.0 μA 3.
PIC16F610/616/16HV610/616 15.6 DC Characteristics: PIC16HV610/616- I (Industrial) DC CHARACTERISTICS Param No. D020 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Conditions Device Characteristics Power-down Base Current(IPD)(2,3) PIC16HV610/616 D021 Min Typ† Max Units — 135 200 μA — 210 280 μA 3.0 — 260 350 μA 4.5 — 135 200 μA 2.0 — 210 285 μA 3.0 VDD Note 2.
PIC16F610/616/16HV610/616 15.7 DC Characteristics: PIC16HV610/616-E (Extended) DC CHARACTERISTICS Param No. D020E Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +125°C for extended Conditions Device Characteristics Power-down Base Current (IPD)(2, 3) PIC16HV610/616 D021E D022E D023E D024E D025E D026E* D027E D028E Min Typ† Max Units VDD Note WDT, BOR, Comparators, VREF and T1OSC disabled — 135 200 μA 2.0 — 210 280 μA 3.
PIC16F610/616/16HV610/616 15.8 DC Characteristics: PIC16F610/616/16HV610/616- I (Industrial) PIC16F610/616/16HV610/616 - E (Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended DC CHARACTERISTICS Param No. Sym VIL Characteristic Min Typ† Max Units Conditions Vss — 0.8 V 4.5V ≤ VDD ≤ 5.5V Vss — 0.15 VDD V 2.0V ≤ VDD ≤ 4.5V 2.0V ≤ VDD ≤ 5.
PIC16F610/616/16HV610/616 15.9 DC Characteristics: PIC16F610/616/16HV610/616- I (Industrial) PIC16F610/616/16HV610/616 - E (Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended DC CHARACTERISTICS Param No.
PIC16F610/616/16HV610/616 15.10 Thermal Considerations Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +125°C Param No. Sym Characteristic Typ Units 70* 85.0* 100* 37* 32.5* 31.0* 31.7* 2.
PIC16F610/616/16HV610/616 15.11 Timing Parameter Symbology The timing parameter symbols have been created with one of the following formats: 1. TppS2ppS 2.
PIC16F610/616/16HV610/616 15.12 AC Characteristics: PIC16F610/616/16HV610/616 (Industrial, Extended) FIGURE 15-6: CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1/CLKIN OS02 OS04 OS04 OS03 OSC2/CLKOUT (LP,XT,HS Modes) OSC2/CLKOUT (CLKOUT Mode) TABLE 15-1: CLOCK OSCILLATOR TIMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +125°C Param No.
PIC16F610/616/16HV610/616 TABLE 15-2: OSCILLATOR PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C ≤ TA ≤ +125°C Param No. Sym Characteristic OS06 TWARM Internal Oscillator Switch when running(3) OS07 INTOSC Internal Calibrated INTOSC Frequency(2) (4MHz) OS08 INTOSC OS10* Internal Calibrated INTOSC Frequency(2) (8MHz) TIOSC ST INTOSC Oscillator Wakeup from Sleep Start-up Time * † Note 1: 2: 3: Freq.
PIC16F610/616/16HV610/616 FIGURE 15-7: CLKOUT AND I/O TIMING Cycle Write Fetch Read Execute Q4 Q1 Q2 Q3 FOSC OS12 OS11 OS20 OS21 CLKOUT OS19 OS18 OS16 OS13 OS17 I/O pin (Input) OS14 OS15 I/O pin (Output) New Value Old Value OS18, OS19 TABLE 15-3: CLKOUT AND I/O TIMING PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C ≤ TA ≤ +125°C Param No.
PIC16F610/616/16HV610/616 FIGURE 15-8: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Start-Up Time Internal Reset(1) Watchdog Timer Reset(1) 31 34 34 I/O pins Note 1: Asserted low.
PIC16F610/616/16HV610/616 TABLE 15-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C ≤ TA ≤ +125°C Param No.
PIC16F610/616/16HV610/616 FIGURE 15-10: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS T0CKI 40 41 42 T1CKI 45 46 49 47 TMR0 or TMR1 TABLE 15-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C ≤ TA ≤ +125°C Param No.
PIC16F610/616/16HV610/616 FIGURE 15-11: CAPTURE/COMPARE/PWM TIMINGS (ECCP) CCP1 (Capture mode) CC01 CC02 CC03 Note: TABLE 15-6: Refer to Figure 15-5 for load conditions. CAPTURE/COMPARE/PWM REQUIREMENTS (ECCP) Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C ≤ TA ≤ +125°C Param No. CC01* CC02* CC03* Sym TccL TccH TccP Characteristic CCP1 Input Low Time CCP1 Input High Time CCP1 Input Period Min Typ† Max Units No Prescaler 0.
PIC16F610/616/16HV610/616 TABLE 15-7: COMPARATOR SPECIFICATIONS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C ≤ TA ≤ +125°C Param No. Sym Characteristics CM01 VOS Input Offset Voltage(2) CM02 VCM Input Common Mode Voltage CM03* CMRR Common Mode Rejection Ratio CM04* TRT Response Time(1) Min Typ† Max Units — ± 5.0 ± 10 mV 0 — VDD – 1.
PIC16F610/616/16HV610/616 TABLE 15-10: SHUNT REGULATOR SPECIFICATIONS (PIC16HV610/616 only) SHUNT REGULATOR CHARACTERISTICS Param No. Symbol Characteristics VSHUNT Shunt Voltage SR01 SR02 ISHUNT SR03* TSETTLE Settling Time SR04 CLOAD Load Capacitance SR05 ΔISNT Regulator operating current * Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +125°C Min Typ Max Units 4.75 5 5.
PIC16F610/616/16HV610/616 TABLE 15-12: PIC16F616/16HV616 A/D CONVERSION REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +125°C Param No. Sym AD130* TAD Characteristic A/D Clock Period A/D Internal RC Oscillator Period AD131 TCNV Conversion Time (not including Acquisition Time)(1) Min Typ† 1.6 — 9.0 μs TOSC-based, VREF ≥ 3.0V 3.0 — 9.0 μs TOSC-based, VREF full range 3.0 6.0 9.0 μs ADCS<1:0> = 11 (ADRC mode) At VDD = 2.5V 1.6 4.
PIC16F610/616/16HV610/616 FIGURE 15-12: PIC16F616/16HV616 A/D CONVERSION TIMING (NORMAL MODE) BSF ADCON0, GO AD134 1 TCY (TOSC/2(1)) AD131 Q4 AD130 A/D CLK 9 A/D Data 8 7 6 3 2 1 0 NEW_DATA OLD_DATA ADRES 1 TCY ADIF GO DONE Note 1: Sampling Stopped AD132 Sample If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed.
PIC16F610/616/16HV610/616 15.13 High Temperature Operation This section outlines the specifications for the PIC16F616 device operating in a temperature range between -40°C and 150°C.(4) The specifications between -40°C and 150°C(4) are identical to those shown in DS41302 and DS80329. Note 1: Writes are not allowed for Program Memory above 125°C. Flash 2: All AC timing specifications are increased by 30%. This derating factor will include parameters such as TPWRT.
PIC16F610/616/16HV610/616 TABLE 15-14: DC CHARACTERISTICS FOR IDD SPECIFICATIONS FOR PIC16F616 – H (High Temp.) Param No. Device Characteristics Condition Units μA D011 μA D012 μA mA D013 μA D014 μA mA D016 μA D017 μA mA D018 μA D019 © 2009 Microchip Technology Inc. Typ Max VDD D010 Supply Current (IDD) Min mA — 13 58 2.0 — 19 67 3.0 — 32 92 5.0 — 135 316 2.0 — 185 400 3.0 — 300 537 5.0 — 240 495 2.0 — 360 680 3.0 — 0.660 1.20 5.0 — 75 158 2.
PIC16F610/616/16HV610/616 TABLE 15-15: DC CHARACTERISTICS FOR IPD SPECIFICATIONS FOR PIC16F616 – H (High Temp.) Param No. Condition Device Characteristics Units Power Down IPD μA Max — 0.05 12 2.0 — 0.15 13 3.0 — 0.35 14 5.0 — 0.5 20 2.0 — 2.5 25 3.0 — 9.5 36 5.0 μA — 5.0 28 3.0 — 6.0 36 5.0 — 105 195 2.0 μA — 110 210 3.0 — 116 220 5.0 — 50 105 2.0 — 55 110 3.0 — 60 125 5.0 — 30 58 2.0 — 45 85 3.0 — 75 142 5.0 — 39 76 2.
PIC16F610/616/16HV610/616 TABLE 15-18: OSCILLATOR PARAMETERS FOR PIC16F616 – H (High Temp.) Param No. OS08 Note 1: Sym Characteristic INTOSC Int. Calibrated INTOSC Freq.(1) Frequency Tolerance Units Min Typ Max ±10% MHz 7.2 8.0 8.8 Conditions 2.0V ≤ VDD ≤ 5.5V -40°C ≤ TA ≤ 150°C To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible. 0.1 µF and 0.01 µF values in parallel are recommended.
PIC16F610/616/16HV610/616 NOTES: DS41288F-page 172 © 2009 Microchip Technology Inc.
PIC16F610/616/16HV610/616 16.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.
PIC16F610/616/16HV610/616 FIGURE 16-3: PIC16F610/616 IDD EC (4 MHz) vs. VDD 1200 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) 1000 Maximum IDD EC (µA) 800 Typical 600 400 200 0 2 1 FIGURE 16-4: 4 3 6 5 VDD (V) PIC16F610/616 IDD XT (1 MHz) vs.
PIC16F610/616/16HV610/616 FIGURE 16-6: PIC16F610/616 IDD INTOSC (4 MHz) vs. VDD 900 Maximum 800 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) IDD INTOSC (µA) 700 Typical 600 500 400 300 200 100 0 2 1 FIGURE 16-7: 3 VDD (V) 4 6 5 PIC16F610/616 IDD INTOSC (8 MHz) vs.
PIC16F610/616/16HV610/616 FIGURE 16-8: PIC16F610/616 IDD EXTRC (4 MHz) vs. VDD 800 Maximum Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) 700 600 IDD EXTRC (µA) Typical 500 400 300 200 100 0 1 2 4 3 5 6 VDD (V) FIGURE 16-9: PIC16F610/616 IDD HS (20 MHz) vs.
PIC16F610/616/16HV610/616 FIGURE 16-10: PIC16F610/616 IPD BASE vs. VDD 9 Extended Typical: Statistical Mean @25°C 8 Industrial: Mean (Worst-Case Temp) + 3σ (-40°C to 85°C) Extended: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) 7 IPD BASE (µA) 6 5 4 3 2 Industrial 1 Typical 0 2 1 4 3 6 5 VDD (V) FIGURE 16-11: PIC16F610/616 IPD COMPARATOR (SINGLE ON) vs.
PIC16F610/616/16HV610/616 FIGURE 16-12: PIC16F610/616 IPD COMPARATOR (BOTH ON) vs. VDD 160 Extended 150 Industrial 140 IPD CMP (µA) 130 120 Typical 110 100 Typical: Statistical Mean @25°C Industrial: Mean (Worst-Case Temp) + 3σ (-40°C to 85°C) Extended: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) 90 80 2 1 4 3 6 5 VDD (V) FIGURE 16-13: PIC16F610/616 IPD WDT vs.
PIC16F610/616/16HV610/616 FIGURE 16-14: PIC16F610/616 IPD BOR vs. VDD 20 Typical: Statistical Mean @25°C Extended Industrial: Mean (Worst-Case Temp) + 3σ (-40°C to 85°C) 18 Extended: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) 16 IPD BOR (µA) 14 Industrial 12 10 8 Typical 6 4 2 0 2 1 4 3 6 5 VDD (V) FIGURE 16-15: PIC16F610/616 IPD CVREF (LOW RANGE) vs.
PIC16F610/616/16HV610/616 FIGURE 16-16: PIC16F610/616 IPD CVREF (HI RANGE) vs. VDD 120 Typical: Statistical Mean @25°C IPD CVREF (µA) Maximum Industrial: Mean (Worst-Case Temp) + 3σ (-40°C to 85°C) Extended: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) 100 80 Typical 60 40 20 0 1 2 3 4 6 5 VDD (V) FIGURE 16-17: PIC16F610/616 IPD T1OSC vs.
PIC16F610/616/16HV610/616 FIGURE 16-18: PIC16F616 IPD A/D vs. VDD 14 Typical: Statistical Mean @25°C 10 IPD A2D (µA) Extended Industrial: Mean (Worst-Case Temp) + 3σ (-40°C to 85°C) Extended: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) 12 8 6 4 Industrial 2 Typical 0 2 1 4 3 6 5 VDD (V) FIGURE 16-19: PIC16HV610/616 IDD LP (32 kHz) vs.
PIC16F610/616/16HV610/616 FIGURE 16-20: PIC16HV610/616 IDD EC (1 MHz) vs. VDD 1000 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) 900 IDD EC (µA) 800 Maximum 700 600 Typical 500 400 300 200 100 2 1 3 5 4 VDD (V) FIGURE 16-21: PIC16HV610/616 IDD EC (4 MHz) vs.
PIC16F610/616/16HV610/616 FIGURE 16-23: PIC16HV610/616 IDD XT (4 MHz) vs. VDD 1400 Maximum Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) 1200 IDD XT (µA) 1000 Typical 800 600 400 200 0 2 1 3 5 4 VDD (V) FIGURE 16-24: PIC16HV610/616 IDD INTOSC (4 MHz) vs.
PIC16F610/616/16HV610/616 FIGURE 16-26: PIC16HV610/616 IDD EXTRC (4 MHz) vs. VDD 1200 IDD EXTRC (µA) Maximum Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) 1000 800 Typical 600 400 200 0 1 2 3 5 4 VDD (V) FIGURE 16-27: PIC16HV610/616 IPD BASE vs.
PIC16F610/616/16HV610/616 FIGURE 16-29: PIC16HV610/616 IPD COMPARATOR (BOTH ON) vs. VDD 600 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) 500 Maximum IPD CMP (µA) 400 Typical 300 200 100 0 2 1 3 5 4 VDD (V) FIGURE 16-30: PIC16HV610/616 IPD WDT vs.
PIC16F610/616/16HV610/616 FIGURE 16-32: PIC16HV610/616 IPD CVREF (LOW RANGE) vs. VDD 500 400 IPD CVREF (µA) Maximum Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) Typical 300 200 100 0 2 1 3 5 4 VDD (V) FIGURE 16-33: PIC16HV610/616 IPD CVREF (HI RANGE) vs.
PIC16F610/616/16HV610/616 FIGURE 16-35: PIC16HV616 IPD A/D vs. VDD Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) 400 350 Maximum 300 IPD A2D (µA) Typical 250 200 150 100 50 0 2 FIGURE 16-36: 3 4 VDD (V) 5 VOL vs. IOL OVER TEMPERATURE (VDD = 3.0V) 0.8 0.7 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) Max. 125°C 0.6 Max. 85°C VOL (V) 0.5 0.4 Typical 25°C 0.3 0.2 Min. -40°C 0.1 0.0 5.0 5.5 6.0 6.5 7.0 7.
PIC16F610/616/16HV610/616 FIGURE 16-37: VOL vs. IOL OVER TEMPERATURE (VDD = 5.0V) 0.45 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) 0.40 Max. 125°C 0.35 Max. 85°C VOL (V) 0.30 0.25 Typ. 25°C 0.20 Min. -40°C 0.15 0.10 0.05 0.00 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 IOL (mA) FIGURE 16-38: VOH vs. IOH OVER TEMPERATURE (VDD = 3.0V) 3.5 3.0 Max. -40°C Typ. 25°C 2.5 Min. 125°C VOH (V) 2.0 1.5 1.
PIC16F610/616/16HV610/616 FIGURE 16-39: VOH vs. IOH OVER TEMPERATURE (VDD = 5.0V) 5.5 5.0 Max. -40°C Typ. 25°C VOH (V) 4.5 Min. 125°C 4.0 3.5 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) 3.0 0.0 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 -3.5 -4.0 -4.5 -5.0 IOH (mA) FIGURE 16-40: TTL INPUT THRESHOLD VIN vs. VDD OVER TEMPERATURE 1.7 1.5 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) Max. -40°C VIN (V) 1.3 Typ.
PIC16F610/616/16HV610/616 FIGURE 16-41: SCHMITT TRIGGER INPUT THRESHOLD VIN vs. VDD OVER TEMPERATURE 4.0 VIH Max. 125°C Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) 3.5 VIH Min. -40°C VIN (V) 3.0 2.5 2.0 VIL Max. -40°C 1.5 VIL Min. 125°C 1.0 0.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 16-42: TYPICAL HFINTOSC START-UP TIMES vs.
PIC16F610/616/16HV610/616 FIGURE 16-43: MAXIMUM HFINTOSC START-UP TIMES vs. VDD OVER TEMPERATURE 25 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) Time (µs) 20 15 85°C 25°C 10 -40°C 5 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 16-44: MINIMUM HFINTOSC START-UP TIMES vs. VDD OVER TEMPERATURE 10 9 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) 8 7 Time (μs) 85°C 6 25°C 5 -40°C 4 3 2 1 0 2.0 2.5 3.0 3.
PIC16F610/616/16HV610/616 FIGURE 16-45: TYPICAL HFINTOSC FREQUENCY CHANGE vs. VDD (25°C) 5 4 Change from Calibration (%) 3 2 1 0 -1 -2 -3 -4 -5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 5.0 5.5 VDD (V) FIGURE 16-46: TYPICAL HFINTOSC FREQUENCY CHANGE vs. VDD (85°C) 5 4 Change from Calibration (%) 3 2 1 0 -1 -2 -3 -4 -5 2.0 2.5 3.0 3.5 4.0 4.5 VDD (V) DS41288F-page 192 © 2009 Microchip Technology Inc.
PIC16F610/616/16HV610/616 FIGURE 16-47: TYPICAL HFINTOSC FREQUENCY CHANGE vs. VDD (125°C) 5 4 Change from Calibration (%) 3 2 1 0 -1 -2 -3 -4 -5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 16-48: TYPICAL HFINTOSC FREQUENCY CHANGE vs. VDD (-40°C) 5 4 Change from Calibration (%) 3 2 1 0 -1 -2 -3 -4 -5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) © 2009 Microchip Technology Inc.
PIC16F610/616/16HV610/616 FIGURE 16-49: 0.6V REFERENCE VOLTAGE vs. TEMP (TYPICAL) 0.61 2.5V Reference Voltage (V) 0.6 3V 4V 0.59 5V 0.58 5.5V 0.57 0.56 -60 -40 -20 0 20 40 60 80 100 120 140 Temp (C) FIGURE 16-50: 1.2V REFERENCE VOLTAGE vs. TEMP (TYPICAL) 1.26 2.5V 1.25 Reference Voltage (V) 3V 1.24 4V 5V 1.23 5.5V 1.22 1.21 1.2 -60 -40 -20 0 20 40 60 80 100 120 140 Temp (C) FIGURE 16-51: SHUNT REGULATOR VOLTAGE vs. INPUT CURRENT (TYPICAL) 5.
PIC16F610/616/16HV610/616 FIGURE 16-52: SHUNT REGULATOR VOLTAGE vs. TEMP (TYPICAL) Shunt Regulator Voltage (V) 5.16 5.14 5.12 5.1 50 mA 5.08 40 mA 5.06 5.04 20 mA 5.02 15 mA 5 10 mA 4.98 4 mA 4.96 -60 -40 -20 0 20 40 60 80 100 120 140 Temp (C) FIGURE 16-53: COMPARATOR RESPONSE TIME (RISING EDGE) 1000 900 Max. 125°C Response Time (nS) 800 700 600 500 Note: Vcm = (VDD - 1.5V)/2 V+ input = Vcm V- input = Transition from Vcm + 100mV to Vcm - 20mV Max. 85°C 400 300 Typ.
PIC16F610/616/16HV610/616 FIGURE 16-54: COMPARATOR RESPONSE TIME (FALLING EDGE) 1000 900 Max. 125°C 800 Response Time (nS) 700 600 500 Note: VCM = (VDD - 1.5V)/2 V+ input = VCM V- input = Transition from VCM - 100MV to VCM + 20MV Max. 85°C 400 300 Typ. 25°C 200 Min. -40°C 100 0 2.0 2.5 4.0 5.5 VDD (V) WDT TIME-OUT PERIOD vs. VDD OVER TEMPERATURE FIGURE 16-55: 55 50 45 40 Time (ms) 35 30 125°C 25 85°C 20 25°C 15 -40°C 10 5 1.5 2 2.5 3 3.5 4 4.5 5 5.
PIC16F610/616/16HV610/616 17.0 PACKAGING INFORMATION 17.1 Package Marking Information 14-Lead PDIP Example XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN 14-Lead SOIC (.150”) XXXXXXXXXXX XXXXXXXXXXX YYWWNNN 14-Lead TSSOP XXXXXXXX YYWW NNN 16-Lead QFN Legend: XX...
PIC16F610/616/16HV610/616 17.2 Package Details The following sections give the technical details of the packages.
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PIC16F610/616/16HV610/616 NOTES: DS41288F-page 204 © 2009 Microchip Technology Inc.
PIC16F610/616/16HV610/616 APPENDIX A: DATA SHEET REVISION HISTORY Revision A This is a new data sheet. Revision B (12/06) Added PIC16F610/16HV610 parts. Replaced Package Drawings. Revision C (03/2007) Replaced Package Drawings (Rev. AM); Replaced Development Support Section; Revised Product ID System. Revision D (06/2008) Added Graphs; Revised 28-Pin ICD Pinout, Electrical Specifications Section; Package Details. Revision E (09/2009) Added section 15.
PIC16F610/616/16HV610/616 APPENDIX B: MIGRATING FROM OTHER PIC® DEVICES This discusses some of the issues in migrating from other PIC® devices to the PIC16F6XX Family of devices. B.
PIC16F610/616/16HV610/616 INDEX A A/D Specifications.................................................... 165, 166 Absolute Maximum Ratings .............................................. 143 AC Characteristics Industrial and Extended ............................................ 157 Load Conditions ........................................................ 156 ADC .................................................................................... 73 Acquisition Requirements ....................................
PIC16F610/616/16HV610/616 Initializing PORTC....................................................... 42 Saving Status and W Registers in RAM ................... 121 Code Protection ................................................................ 125 Comparator C2OUT as T1 Gate ..................................................... 65 Operation .................................................................... 57 Operation During Sleep .............................................. 61 Response Time .........
PIC16F610/616/16HV610/616 Context Saving.......................................................... 121 Interrupt-on-Change.................................................... 34 PORTA Interrupt-on-Change .................................... 119 RA2/INT .................................................................... 118 Timer0....................................................................... 119 TMR1 ..........................................................................
PIC16F610/616/16HV610/616 Reset Values (special registers) ............................... 117 Special Function Registers ......................................... 14 Special Register Summary ......................................... 17 SRCON0 (SR Latch Control 0) ................................... 69 SRCON1 (SR Latch Control 1) ................................... 69 STATUS ...................................................................... 18 T1CON ......................................................
PIC16F610/616/16HV610/616 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers.
PIC16F610/616/16HV610/616 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document.
PIC16F610/616/16HV610/616 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX XXX Device Temperature Range Package Pattern Examples: a) b) Device: PIC16F610/616/16HV610/616, PIC16F610/616/16HV610/ 616T(1) c) d) e) Temperature Range: I E H = -40°C to +85°C = -40°C to +125°C = -40°C to +150°C (Industrial) (Extended) (High Temp.
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