Datasheet
PIC12F609/12F615/12F617/16F610/16F616 AND PIC12HV609/12HV615/16HV610/16HV616
DS41396A-page 8 2009 Microchip Technology Inc.
4.1.3 ERASE ALGORITHMS
The PIC12F609/12F615/12F617/16F610/16F616 and
PIC12HV609/12HV615/16HV610/16HV616 devices will
erase different memory locations depending on the PC
and CP
. The following sequences can be used to erase
noted memory locations. To erase the program memory
and Configuration Word (0x2007), the following sequence
must be performed. Note the Calibration Word (0x2008)
and User ID (0x2000-0x2003) will not be erased.
1. Do a Bulk Erase Program Memory command.
2. Wait T
ERA to complete erase.
To erase the User ID (0x2000-0x2003), Configuration
Word (0x2007) and program memory, use the following
sequence. Note that the Calibration Word (0x2008) will
not be erased.
1. Perform Load Configuration with dummy data to
point the PC to 0x2000.
2. Perform a Bulk Erase Program Memory
command.
3. Wait T
ERA to complete erase.
4.1.4 SERIAL PROGRAM/VERIFY
OPERATION
The ICSPCLK pin is used as a clock input and the
ICSPDAT pin is used for entering command bits and
data input/output during serial operation. To input a
command, ICSPCLK is cycled six times. Each
command bit is latched on the falling edge of the clock
with the LSb of the command being input first. The data
input onto the ICSPDAT pin is required to have a mini-
mum setup and hold time (see Table 7-1), with respect
to the falling edge of the clock. Commands that have
data associated with them (Read and Load) are
specified to have a minimum delay of 1 s between the
command and the data. After this delay, the clock pin is
cycled 16 times with the first cycle being a Start bit and
the last cycle being a Stop bit.
During a read operation, the LSb will be transmitted
onto the ICSPDAT pin on the rising edge of the second
cycle. For a load operation, the LSb will be latched on
the falling edge of the second cycle. A minimum 1 s
delay is also specified between consecutive
commands, except for the End Programming
command, which requires a 100 s (T
DIS).
All commands and data words are transmitted LSb first.
Data is transmitted on the rising edge and latched on
the falling edge of the ICSPCLK. To allow for decoding
of commands and reversal of data pin configuration, a
time separation of at least 1 s (T
DLY1) is required
between a command and a data word.
The commands that are available are described in
Table 4-1.