Datasheet

 2009 Microchip Technology Inc. DS41396A-page 23
PIC12F609/12F615/12F617/16F610/16F616 AND PIC12HV609/12HV615/16HV610/16HV616
7.0 PROGRAM/VERIFY MODE ELECTRICAL CHARACTERISTICS
TABLE 7-1: AC/DC CHARACTERISTICS TIMING REQUIREMENTS FOR PROGRAM/VERIFY
MODE
AC/DC CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Operating Temperature -40°C  TA +85°C
Operating Voltage 4.5V  V
DD 5.5V
Sym. Characteristics Min. Typ. Max. Units Conditions/Comments
General
V
DD VDD level for read/write operations,
program and data memory
2.0 — 5.5 V PIC16F616/F610,
PIC12F615/F617/F609
2.0 — 4.7
(1)
V PIC16HV616/HV610,
PIC12HV615/HV609
2.0 — 5.25
(2)
V PIC16HV616/HV610,
PIC12HV615/HV609
V
DD level for bulk erase operations,
program and data memory
4.5 — 5.5 V PIC16F616/F610,
PIC12F615/F617/F609
4.5 — 4.7
(1)
V PIC16HV616/HV610,
PIC12HV615/HV609
4.5 — 5.25
(2)
V PIC16HV616/HV610,
PIC12HV615/HV609
VIHH High voltage on MCLR for
Program/Verify mode entry
10 — 13 V
IIHH MCLR current during programming — 300 1000 A
T
VHHR MCLR rise time (VSS to VHH) for
Program/Verify mode entry
——1.0s
T
PPDP Hold time after VPPchanges 5 — — s
V
IH1 (ICSPCLK, ICSPDAT) input high level 0.8 VDD —— V
VIL1 (ICSPCLK, ICSPDAT) input low level 0.2 VDD —— V
TSET0 ICSPCLK, ICSPDAT setup time
before MCLR
 (Program/Verify mode
selection pattern setup time)
100 — — ns
T
HLD0 Hold time after VDD changes 5 — — s
Serial Program/Verify
T
SET1 Data in setup time before clock 100 — — ns
T
HLD1 Data in hold time after clock 100 — — ns
T
DLY1 Data input not driven to next clock
input (delay required between
command/data or command/
command)
1.0 — — s
T
DLY2 Delay between clockto clockof
next command or data
1.0 — — s
T
DLY3Clock to data out valid (during a
Read Data command)
——80ns
T
ERA Erase cycle time — 5 6 ms
T
PROG Programming cycle time 3 — — ms 10°C  TA +40°C
T
DIS Time delay from program to compare
(HV discharge time)
100 — — s
Note 1: Maximum VDD voltage when programming the device without a current limiting series resistor. Voltages above this level
will cause the shunt regulator to draw excessive current and damage the device.
2: Limiting the current through the shunt regulator to within max shunt current (device electrical characteristic SR02) with
either a series resistor or with a current limited supply.