PIC16F5X Data Sheet Flash-Based, 8-Bit CMOS Microcontroller Series © 2007 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
PIC16F5X Flash-Based, 8-Bit CMOS Microcontroller Series High-Performance RISC CPU: Low-Power Features: • Only 33 single-word instructions to learn • All instructions are single cycle except for program branches which are two-cycle • Two-level deep hardware stack • Direct, Indirect and Relative Addressing modes for data and instructions • Operating speed: - DC – 20 MHz clock speed - DC – 200 ns instruction cycle time • On-chip Flash program memory: - 512 x 12 on PIC16F54 - 2048 x 12 on PIC16F57 - 2048 x 12
PIC16F5X Pin Diagrams PDIP, SOIC 18 17 16 15 14 13 12 11 10 RA1 RA0 OSC1/CLKIN OSC2/CLKOUT VDD RB7/ICSPDAT RB6/ICSPCLK RB5 RB4 T0CKI •1 28 MCLR/VPP VDD 2 27 OSC1/CLKIN N/C 3 26 VSS 4 25 OSC2/CLKOUT RC7 N/C 5 24 RC6 RA0 6 23 RA1 7 RA2 8 21 RC5 RC4 RC3 RA3 9 20 RC2 RB0 10 19 RC1 RB1 11 18 RC0 RB2 12 17 RB7/ICSPDAT RB3 13 16 RB6/ICSPCLK RB4 14 15 RB5 PIC16F57 •1 2 3 4 5 6 7 8 9 RA2 RA3 T0CKI MCLR/VPP VSS RB0 RB1 RB2 RB3 PIC16F54 PDIP, SOIC 22 SSOP SS
PIC16F5X Table of Contents 1.0 General Description...................................................................................................................................................................... 5 2.0 Architectural Overview ................................................................................................................................................................. 7 3.0 Memory Organization ..............................................................................
PIC16F5X NOTES: DS41213D-page 4 © 2007 Microchip Technology Inc.
PIC16F5X 1.0 GENERAL DESCRIPTION 1.1 The PIC16F5X from Microchip Technology is a family of low-cost, high-performance, 8-bit, fully static, Flashbased CMOS microcontrollers. It employs a RISC architecture with only 33 single-word/single-cycle instructions. All instructions are single cycle except for program branches which take two cycles. The PIC16F5X delivers performance an order of magnitude higher than its competitors in the same price category.
PIC16F5X NOTES: DS41213D-page 6 © 2007 Microchip Technology Inc.
PIC16F5X 2.0 ARCHITECTURAL OVERVIEW The high performance of the PIC16F5X family can be attributed to a number of architectural features commonly found in RISC microprocessors. To begin with, the PIC16F5X uses a Harvard architecture in which program and data are accessed on separate buses. This improves bandwidth over traditional von Neumann architecture where program and data are fetched on the same bus.
PIC16F5X FIGURE 2-1: Flash 512 X 12 (F54) 2048 X 12(F57) 2048 x 12(F59) PIC16F5X SERIES BLOCK DIAGRAM 9-11 9-11 T0CKI Pin Stack 1 Stack 2 OSC1 OSC2 MCLR Configuration Word “Disable” “Osc Select” PC Watchdog Timer 12 2 “CodeProtect” Oscillator/ Timing & Control Instruction Register 9 CLKOUT WDT/TMR0 Prescaler WDT Time-out 12 8 “Sleep” Instruction Decoder 6 “Option” Option Reg.
PIC16F5X TABLE 2-1: PIC16F54 PINOUT DESCRIPTION Function Input Type Output Type RA0 RA0 TTL CMOS Bidirectional I/O pin RA1 RA1 TTL CMOS Bidirectional I/O pin RA2 RA2 TTL CMOS Bidirectional I/O pin RA3 RA3 TTL CMOS Bidirectional I/O pin RB0 RB0 TTL CMOS Bidirectional I/O pin RB1 RB1 TTL CMOS Bidirectional I/O pin RB2 RB2 TTL CMOS Bidirectional I/O pin RB3 RB3 TTL CMOS Bidirectional I/O pin RB4 RB4 TTL CMOS Bidirectional I/O pin RB5 RB5 TTL CMOS Bidirection
PIC16F5X TABLE 2-2: PIC16F57 PINOUT DESCRIPTION Function Input Type Output Type RA0 RA0 TTL CMOS Bidirectional I/O pin RA1 RA1 TTL CMOS Bidirectional I/O pin RA2 RA2 TTL CMOS Bidirectional I/O pin RA3 RA3 TTL CMOS Bidirectional I/O pin RB0 RB0 TTL CMOS Bidirectional I/O pin RB1 RB1 TTL CMOS Bidirectional I/O pin RB2 RB2 TTL CMOS Bidirectional I/O pin RB3 RB3 TTL CMOS Bidirectional I/O pin RB4 RB4 TTL CMOS Bidirectional I/O pin RB5 RB5 TTL CMOS Bidirection
PIC16F5X TABLE 2-3: PIC16F59 PINOUT DESCRIPTION Function Input Type Output Type RA0 RA0 TTL CMOS Bidirectional I/O pin RA1 RA1 TTL CMOS Bidirectional I/O pin RA2 RA2 TTL CMOS Bidirectional I/O pin RA3 RA3 TTL CMOS Bidirectional I/O pin RB0 RB0 TTL CMOS Bidirectional I/O pin RB1 RB1 TTL CMOS Bidirectional I/O pin RB2 RB2 TTL CMOS Bidirectional I/O pin RB3 RB3 TTL CMOS Bidirectional I/O pin RB4 RB4 TTL CMOS Bidirectional I/O pin RB5 RB5 TTL CMOS Bidirection
PIC16F5X 2.1 Clocking Scheme/Instruction Cycle 2.2 Instruction Flow/Pipelining An instruction cycle consists of four Q cycles (Q1, Q2, Q3 and Q4). The instruction fetch and execute are pipelined such that fetch takes one instruction cycle, while decode and execute takes another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the Program Counter to change (e.g.
PIC16F5X 3.0 MEMORY ORGANIZATION PIC16F5X memory is organized into program memory and data memory. For the PIC16F57 and PIC16F59, which have more than 512 words of program memory, a paging scheme is used. Program memory pages are accessed using one or two STATUS register bits. For the PIC16F57 and PIC16F59, which have a data memory register file of more than 32 registers, a banking scheme is used. Data memory banks are accessed using the File Selection Register (FSR).
PIC16F5X 3.2 3.2.1 Data Memory Organization Data memory is composed of registers or bytes of RAM. Therefore, data memory for a device is specified by its register file. The register file is divided into two functional groups: Special Function Registers (SFR) and General Purpose Registers (GPR). GENERAL PURPOSE REGISTER FILE The register file is accessed either directly or indirectly through the File Select Register (FSR). The FSR register is described in Section 3.
PIC16F5X FIGURE 3-5: PIC16F59 REGISTER FILE MAP FSR<7:5> 000 001 010 011 100 101 110 111 File Address 00h INDF(1) 01h TMR0 02h PCL 03h STATUS 04h FSR 05h PORTA 06h PORTB 07h PORTC 08h PORTD 09h PORTE 20h 40h 60h 80h A0h C0h E0h Addresses map back to addresses in Bank 0.
PIC16F5X 3.2.2 SPECIAL FUNCTION REGISTERS The Special Function Registers (SFR) are registers used by the CPU and peripheral functions to control the operation of the device (Table 3-1). The Special Function Registers can be classified into two sets. The Special Function Registers associated with the “core” functions are described in this section. Those related to the operation of the peripheral features are described in the section for each peripheral feature.
PIC16F5X 3.3 STATUS Register This register contains the arithmetic status of the ALU, the Reset status and the page preselect bits for program memories larger than 512 words. The STATUS register can be the destination for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic.
PIC16F5X 3.4 Option Register The Option register is a 6-bit wide, write-only register which contains various control bits to configure the Timer0/WDT prescaler and Timer0. By executing the OPTION instruction, the contents of the W register will be transferred to the Option register. A Reset sets the Option<5:0> bits.
PIC16F5X 3.5 FIGURE 3-7: Program Counter As a program instruction is executed, the Program Counter (PC) will contain the address of the next program instruction to be executed. The PC value is increased by one, every instruction cycle, unless an instruction changes the PC. LOADING OF PC BRANCH INSTRUCTIONS – PIC16F57 AND PIC16F59 GOTO Instruction 10 9 8 7 PCL For a GOTO instruction, bits 8:0 of the PC are provided by the GOTO instruction word.
PIC16F5X 3.6 Stack The PIC16F54 device has a 9-bit wide, two-level hardware PUSH/POP stack. The PIC16F57 and PIC16F59 devices have an 11-bit wide, two-level hardware PUSH/POP stack. A CALL instruction will PUSH the current value of stack 1 into stack 2 and then PUSH the current program counter value, incremented by one, into stack level 1. If more than two sequential CALL’s are executed, only the most recent two return addresses are stored.
PIC16F5X 4.0 OSCILLATOR CONFIGURATIONS 4.1 Oscillator Types TABLE 4-1: Osc Type The PIC16F5X devices can be operated in four different oscillator modes. The user can program two Configuration bits (FOSC1:FOSC0) to select one of these four modes: • • • • LP: XT: HS: RC: Low-power Crystal Crystal/Resonator High-speed Crystal/Resonator Resistor/Capacitor 4.
PIC16F5X 4.3 External Crystal Oscillator Circuit FIGURE 4-4: Either a pre-packaged oscillator or a simple oscillator circuit with TTL gates can be used as an external crystal oscillator circuit. Pre-packaged oscillators provide a wide operating range and better stability. A well designed crystal oscillator will provide good performance with TTL gates. Two types of crystal oscillator circuits can be used: one with parallel resonance or one with series resonance.
PIC16F5X 5.0 RESET The TO and PD bits (STATUS <4:3>) are set or cleared depending on the different Reset conditions (Table 5-1). These bits may be used to determine the nature of the Reset. The PIC16F5X devices may be reset in one of the following ways: • • • • • Power-on Reset (POR) MCLR Reset (normal operation) MCLR Wake-up Reset (from Sleep) WDT Reset (normal operation) WDT Wake-up Reset (from Sleep) Table 5-3 lists a full description of Reset states of all registers.
PIC16F5X TABLE 5-3: RESET CONDITIONS FOR ALL REGISTERS Register Address Power-on Reset MCLR or WDT Reset W N/A xxxx xxxx uuuu uuuu TRIS N/A 1111 1111 1111 1111 OPTION N/A --11 1111 --11 1111 INDF 00h xxxx xxxx uuuu uuuu TMR0 01h xxxx xxxx uuuu uuuu PCL 02h 1111 1111 1111 1111 STATUS 03h 0001 1xxx 000q quuu (1) FSR 04h 111x xxxx 111u uuuu FSR(2) 04h 1xxx xxxx 1uuu uuuu FSR(3) 04h xxxx xxxx uuuu uuuu PORTA 05h ---- xxxx ---- uuuu PORTB 06h xxxx xxxx uuuu uu
PIC16F5X 5.1 Power-on Reset (POR) The PIC16F5X family of devices incorporate on-chip Power-on Reset (POR) circuitry which provides an internal chip Reset for most power-up situations. To use this feature, the user merely ties the MCLR/VPP pin to VDD. A simplified block diagram of the on-chip Power-on Reset circuit is shown in Figure 5-1. The Power-on Reset circuit and the Device Reset Timer (Section 5.2) circuit are closely related. On power-up, the Reset latch is set and the DRT is reset.
PIC16F5X FIGURE 5-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD) VDD MCLR Internal POR TDRT DRT Time-out Internal Reset TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): FAST VDD RISE TIME FIGURE 5-4: VDD MCLR Internal POR TDRT DRT Time-out Internal Reset TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): SLOW VDD RISE TIME FIGURE 5-5: V1 VDD MCLR Internal POR TDRT DRT Time-out Internal Reset Note : When VDD rises slowly, the TDRT time-out expires long before VDD has reached its final
PIC16F5X 5.2 Device Reset Timer (DRT) FIGURE 5-7: The Device Reset Timer (DRT) provides an 18 ms nominal time-out on Reset regardless of the oscillator mode used. The DRT operates on an internal RC oscillator. The processor is kept in Reset as long as the DRT is active. The DRT delay allows VDD to rise above VDD min. and for the chosen oscillator to stabilize. Oscillator circuits, based on crystals or ceramic resonators, require a certain time after power-up to establish a stable oscillation.
PIC16F5X NOTES: DS41213D-page 28 © 2007 Microchip Technology Inc.
PIC16F5X 6.0 I/O PORTS As with any other register, the I/O registers can be written and read under program control. However, read instructions (e.g., MOVF PORTB, W) always read the I/O pins independent of the pin’s Input/Output modes. On Reset, all I/O ports are defined as input (inputs are at high-impedance), since the I/O control registers (TRISA, TRISB, TRISC, TRISD and TRISE) are all set. 6.1 6.
PIC16F5X TABLE 6-1: Address SUMMARY OF PORT REGISTERS Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Power-on Reset Value on MCLR and WDT Reset N/A TRIS 05h PORTA I/O Control Registers (TRISA, TRISB, TRISC, TRISD and TRISE) 1111 1111 1111 1111 06h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu 07h PORTC(1) RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx uuuu uuuu 08h PORTD(2) RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx xxxx uuuu uuuu 09h PORTE(
PIC16F5X 6.8 6.8.1 EXAMPLE 6-1: I/O Programming Considerations BIDIRECTIONAL I/O PORTS Some instructions operate internally as read followed by write operations. The BCF and BSF instructions, for example, read the entire port into the CPU, execute the bit operation and re-write the result. Caution must be used when these instructions are applied to a port where one or more pins are used as input/outputs.
PIC16F5X NOTES: DS41213D-page 32 © 2007 Microchip Technology Inc.
PIC16F5X 7.0 TIMER0 MODULE AND TMR0 REGISTER Counter mode is selected by setting the T0CS bit (OPTION<5>). In this mode, Timer0 will increment either on every rising or falling edge of pin T0CKI. The incrementing edge is determined by the source edge select bit T0SE (OPTION<4>). Clearing the T0SE bit selects the rising edge. Restrictions on the external clock input are discussed in detail in Section 7.1 “Using Timer0 with an External Clock”.
PIC16F5X FIGURE 7-3: TIMER0 TIMING: INTERNAL CLOCK/PRESCALER 1:2 PC (Program Counter) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Instruction Fetch MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W Timer0 PC - 1 PC T0 PC + 1 PC + 3 T0 + 1 Write TMR0 executed TABLE 7-1: PC + 4 PC + 5 Read TMR0 reads NT0 Read TMR0 reads NT0 PC + 6 NT0 + 1 NT0 Instruction Execute Address PC + 2 Read TMR0 reads NT0 Read TMR0 reads
PIC16F5X 7.1 Using Timer0 with an External Clock When a prescaler is used, the external clock input is divided by the asynchronous ripple counter-type prescaler so that the prescaler output is symmetrical. For the external clock to meet the sampling requirement, the ripple counter must be taken into account. Therefore, it is necessary for T0CKI to have a period of at least 4TOSC (and a small RC delay of 40 ns) divided by the prescaler value.
PIC16F5X 7.2.1 SWITCHING PRESCALER ASSIGNMENT To change prescaler from the WDT to the Timer0 module, use the sequence shown in Example 7-2. This sequence must be used even if the WDT is disabled. A CLRWDT instruction should be executed before switching the prescaler. The prescaler assignment is fully under software control (i.e., it can be changed “on-the-fly” during program execution).
PIC16F5X 8.0 SPECIAL FEATURES OF THE CPU What sets a microcontroller apart from other processors are special circuits that deal with the needs of realtime applications. The PIC16F5X family of microcontrollers have a host of such features intended to maximize system reliability, minimize cost through elimination of external components, provide powersaving operating modes and offer code protection.
PIC16F5X 8.2 8.2.2 Watchdog Timer (WDT) The Watchdog Timer (WDT) is a free running on-chip RC oscillator which does not require any external components. This RC oscillator is separate from the RC oscillator of the OSC1/CLKIN pin. That means that the WDT will run even if the clock on the OSC1/CLKIN and OSC2/CLKOUT pins have been stopped, for example, by execution of a SLEEP instruction. During normal operation or Sleep, a WDT Reset or Wake-up Reset generates a device Reset.
PIC16F5X 8.3 Power-Down Mode (Sleep) A device may be powered down (Sleep) and later powered up (wake-up from Sleep). 8.3.1 SLEEP The Power-down mode is entered by executing a SLEEP instruction. If enabled, the Watchdog Timer will be cleared but keeps running, the TO bit (STATUS<4>) is set, the PD bit (STATUS<3>) is cleared and the oscillator driver is turned off. The I/O ports maintain the status they had before the SLEEP instruction was executed (driving high, driving low or high-impedance).
PIC16F5X FIGURE 8-1: TYPICAL IN-CIRCUIT SERIAL PROGRAMMING™ CONNECTION External Connector Signals To Normal Connections PIC16F5X +5V VDD 0V VSS VPP MCLR/VPP CLK RB6/ICSPCLK Data I/O RB7/ICSPDAT VDD To Normal Connections DS41213D-page 40 © 2007 Microchip Technology Inc.
PIC16F5X 9.0 INSTRUCTION SET SUMMARY Each PIC16F5X instruction is a 12-bit word divided into an opcode, which specifies the instruction type, and one or more operands which further specify the operation of the instruction. The PIC16F5X instruction set summary in Table 9-2 groups the instructions into byteoriented, bit-oriented, and literal and control operations. Table 9-1 shows the opcode field descriptions.
PIC16F5X TABLE 9-2: Mnemonic, Operands INSTRUCTION SET SUMMARY 12-Bit Opcode Description Cycles MSb LSb Status Notes Affected ADDWF 0001 11df ffff C,DC,Z 1, 2, 4 f, d Add W and f 1 ANDWF 0001 01df ffff f, d AND W with f 1 Z 2, 4 CLRF 0000 011f ffff f Clear f 1 Z 4 CLRW 0000 0100 0000 — Clear W 1 Z COMF 0010 01df ffff f, d Complement f 1 Z DECF 0000 11df ffff f, d Decrement f 1 Z 2, 4 DECFSZ 0010 11df ffff f, d Decrement f, Skip if 0 1(2) None 2, 4 1 INCF 0010 10df ffff f, d Increment f Z 2, 4 1(2) INCF
PIC16F5X ADDWF Add W and f ANDWF Syntax: [ label ] ADDWF Syntax: [ label ] ANDWF Operands: 0 ≤ f ≤ 31 d ∈ [0,1] Operands: 0 ≤ f ≤ 31 d ∈ [0,1] Operation: (W) + (f) → (dest) Operation: (W) .AND. (f) → (dest) Status Affected: C, DC, Z Status Affected: Z Encoding: 0001 11df f, d AND W with f ffff Encoding: 0001 01df f, d ffff Description: Add the contents of the W register and register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register.
PIC16F5X BSF Bit Set f BTFSS Syntax: [ label ] BSF Syntax: [ label ] BTFSS f, b Operands: 0 ≤ f ≤ 31 0≤b≤7 Operands: 0 ≤ f ≤ 31 0≤b<7 Operation: 1 → (f) Operation: skip if (f) = 1 Status Affected: None Status Affected: None Encoding: 0101 f, b Bit Test f, Skip if Set bbbf Description: Bit ‘b’ in register ‘f’ is set.
PIC16F5X CALL Subroutine Call CLRW Syntax: [ label ] CALL k Syntax: [ label ] CLRW Operands: 0 ≤ k ≤ 255 Operands: None Operation: (PC) + 1→ TOS; k → PC<7:0>; (Status<6:5>) → PC<10:9>; 0 → PC<8> Operation: 00h → (W); 1→Z Status Affected: Z Status Affected: Encoding: Description: None 1001 kkkk kkkk Subroutine call. First, return address (PC + 1) is pushed onto the stack. The eight-bit immediate address is loaded into PC bits <7:0>.
PIC16F5X COMF Complement f DECFSZ Syntax: [ label ] COMF Syntax: [ label ] DECFSZ f, d Operands: 0 ≤ f ≤ 31 d ∈ [0,1] Operands: 0 ≤ f ≤ 31 d ∈ [0,1] Operation: (f) → (dest) Operation: (f) – 1 → d; Status Affected: Z Status Affected: None Encoding: 0010 01df f, d Decrement f, Skip if 0 ffff Description: The contents of register ‘f’ are complemented. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’.
PIC16F5X GOTO Unconditional Branch INCFSZ Syntax: [ label ] Syntax: [ label ] Operands: 0 ≤ k ≤ 511 Operands: Operation: k → PC<8:0>; STATUS<6:5> → PC<10:9> 0 ≤ f ≤ 31 d ∈ [0,1] Operation: (f) + 1 → (dest), skip if result = 0 None Status Affected: None Status Affected: Encoding: Description: GOTO k 101k kkkk kkkk GOTO is an unconditional branch. The 9-bit immediate value is loaded into PC bits <8:0>. The upper bits of PC are loaded from STATUS<6:5>. GOTO is a twocycle instruction.
PIC16F5X IORLW Inclusive OR literal with W MOVF Syntax: [ label ] Syntax: [ label ] Operands: 0 ≤ k ≤ 255 Operands: Operation: (W) .OR. (k) → (W) 0 ≤ f ≤ 31 d ∈ [0,1] Status Affected: Z Operation: (f) → (dest) Status Affected: Z Encoding: Description: 1101 IORLW k kkkk kkkk The contents of the W register are OR’ed with the eight-bit literal ‘k’. The result is placed in the W register.
PIC16F5X MOVWF Move W to f Syntax: [ label ] Operands: 0 ≤ f ≤ 31 Operands: None Operation: (W) → (f) Operation: (W) → OPTION Status Affected: None Status Affected: None Encoding: 0000 MOVWF 001f f ffff Description: Move data from the W register to register ‘f’.
PIC16F5X RLF Rotate Left f through Carry RRF Syntax: [ label ] RLF Syntax: [ label ] Operands: 0 ≤ f ≤ 31 d ∈ [0,1] Operands: 0 ≤ f ≤ 31 d ∈ [0,1] Operation: See description below Operation: See description below Status Affected: C Status Affected: C Encoding: Description: 0011 f, d 01df ffff The contents of register ‘f’ are rotated one bit to the left through the Carry Flag (STATUS<0>). If ‘d’ is ‘0’, the result is placed in the W register.
PIC16F5X SUBWF Subtract W from f SWAPF Syntax: [ label ] SUBWF f, d Syntax: [ label ] SWAPF f, d Operands: 0 ≤ f ≤ 31 d ∈ [0,1] Operands: 0 ≤ f ≤ 31 d ∈ [0,1] Operation: (f) – (W) → (dest) Operation: Status Affected: C, DC, Z (f<3:0>) → (dest<7:4>); (f<7:4>) → (dest<3:0>) Status Affected: None Encoding: Description: 0000 10df ffff Subtract (2’s complement method) the W register from register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register.
PIC16F5X XORLW Exclusive OR literal with W Syntax: [ label ] XORLW k Operands: 0 ≤ k ≤ 255 Operation: (W) .XOR. k → (W) Status Affected: Z Encoding: 1111 kkkk kkkk Description: The contents of the W register are XOR’ed with the eight-bit literal ‘k’. The result is placed in the W register.
PIC16F5X 10.
PIC16F5X 10.2 MPASM Assembler The MPASM Assembler is a full-featured, universal macro assembler for all PIC MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel® standard HEX files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging.
PIC16F5X 10.7 MPLAB ICE 2000 High-Performance In-Circuit Emulator The MPLAB ICE 2000 In-Circuit Emulator is intended to provide the product development engineer with a complete microcontroller design tool set for PIC microcontrollers. Software control of the MPLAB ICE 2000 In-Circuit Emulator is advanced by the MPLAB Integrated Development Environment, which allows editing, building, downloading and source debugging from a single environment.
PIC16F5X 10.11 PICSTART Plus Development Programmer 10.13 Demonstration, Development and Evaluation Boards The PICSTART Plus Development Programmer is an easy-to-use, low-cost, prototype programmer. It connects to the PC via a COM (RS-232) port. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. The PICSTART Plus Development Programmer supports most PIC devices in DIP packages up to 40 pins.
PIC16F5X 11.0 ELECTRICAL SPECIFICATIONS FOR PIC16F54/57 Absolute Maximum Ratings(†) Ambient Temperature under bias ......................................................................................................... -40°C to +125°C Storage Temperature ........................................................................................................................... -65°C to +150°C Voltage on VDD with respect to VSS ..............................................................................
PIC16F5X 11.0 ELECTRICAL SPECIFICATIONS FOR PIC16F59 (continued) Absolute Maximum Ratings(†) Ambient Temperature under bias .........................................................................................................-40°C to +125°C Storage Temperature............................................................................................................................-65°C to +150°C Voltage on VDD with respect to VSS .......................................................................
PIC16F5X PIC16F5X VOLTAGE-FREQUENCY GRAPH, -40°C ≤ TA ≤ +125°C FIGURE 11-1: 5.5 5.0 4.5 VDD (Volts) 4.0 3.5 3.0 2.5 2.0 0 4 8 10 12 16 20 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. © 2007 Microchip Technology Inc.
PIC16F5X 11.1 DC Characteristics: PIC16F5X (Industrial) DC CHARACTERISTICS Standard Operating Conditions (unless otherwise specified) Operating Temperature -40°C ≤ TA ≤ +85°C for industrial Param Sym. No. Min. Typ† Max. Units Characteristic/Device Conditions D001 VDD Supply Voltage 2.0 — 5.5 V D002 VDR RAM Data Retention Voltage(1) — 1.5* — V Device in Sleep mode D003 VPOR VDD Start Voltage to ensure Power-on Reset — Vss — V See Section 5.
PIC16F5X 11.2 DC Characteristics: PIC16F5X (Extended) Standard Operating Conditions (unless otherwise specified) Operating Temperature -40°C ≤ TA ≤ +125°C for extended DC CHARACTERISTICS Param Sym. No. D001 VDD Characteristic/Device Supply Voltage RAM Data Retention Voltage D002 VDR D003 VPOR VDD Start Voltage to ensure Power-on Reset D004 SVDD VDD Rise Rate to ensure Power-on Reset D010 IDD D020 IPD (1) Min. Typ† 2.0 — Max. Units 5.5 Conditions V — 1.
PIC16F5X 11.3 DC Characteristics PIC16F5X DC CHARACTERISTICS Param Sym. No. VIL D030 Characteristic VIH Min. Typ† Max. Units VSS VSS VSS VSS VSS VSS VSS VSS — — — — — — — — 0.8V 0.15 VDD 0.15 VDD 0.15 VDD 0.15 VDD 0.3 VDD 0.3 0.3 V V V V V V V V 4.5V
PIC16F5X 11.4 Timing Parameter Symbology and Load Conditions The timing parameter symbols have been created with one of the following formats: 1. TppS2ppS 2.
PIC16F5X TABLE 11-1: EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions (unless otherwise specified) AC CHARACTERISTICS Operating Temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Parameter No. Sym. FOSC Characteristic External CLKIN Frequency(1) Oscillator Frequency(1) 1 TOSC External CLKIN Period(1) Oscillator Period(1) Min. Typ† Max. Units DC — 4.0 MHz XT Osc mode DC — 20 MHz HS Osc mode DC — 200 kHz DC — 4.0 MHz RC Osc mode 0.
PIC16F5X FIGURE 11-4: CLKOUT AND I/O TIMING – PIC16F5X Q1 Q4 Q2 Q3 OSC1 11 10 CLKOUT 13 14 12 18 19 16 I/O Pin (input) 15 17 I/O Pin (output) New Value Old Value 20, 21 Note: TABLE 11-2: Param No. Please refer to Figure 11-2 for load conditions. CLKOUT AND I/O TIMING REQUIREMENTS – PIC16F5X Sym. Characteristic Min. Typ† Max. Units 15 30** ns 10 TosH2CKL OSC1↑ to CLKOUT↓(1) — 11 TosH2CKH OSC1↑ to CLKOUT↑(1) — 15 30** ns 12 TCKR CLKOUT rise time(1) — 5.
PIC16F5X FIGURE 11-5: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER TIMING -– PIC16F5X VDD MCLR 30 Internal POR 32 32 32 DRT Time-out Internal RESET Watchdog Timer Reset 31 34 34 I/O pin(1) Note 1: Please refer to Figure 11-2 for load conditions. TABLE 11-3: RESET, WATCHDOG TIMER AND DEVICE RESET TIMER – PIC16F5X Standard Operating Conditions (unless otherwise specified) Operating Temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended AC CHARACTERISTICS Param Sym. No.
PIC16F5X FIGURE 11-6: TIMER0 CLOCK TIMINGS – PIC16F5X T0CKI 40 41 42 Note: Please refer to Figure 11-2 for load conditions. TABLE 11-4: TIMER0 CLOCK REQUIREMENTS – PIC16F5X Standard Operating Conditions (unless otherwise specified) Operating Temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended AC CHARACTERISTICS Param No. 40 41 Sym. Min. Typ† Max. Units Tt0H T0CKI High Pulse Width: No Prescaler 0.5 TCY + 20* — — ns With Prescaler 10* — — ns 0.
PIC16F5X NOTES: DS41213D-page 68 © 2007 Microchip Technology Inc.
PIC16F5X 12.0 PACKAGING INFORMATION 12.1 Package Marketing Information 18-Lead PDIP Example XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX PIC16F54 -I/P e3 YYWWNNN 0723CBA 18-Lead SOIC Example XXXXXXXXXXXX XXXXXXXXXXXX XXXXXXXXXXXX PIC16F54 -E/SO e3 0718CDK YYWWNNN Example 20-Lead SSOP XXXXXXXXXXX XXXXXXXXXXX YYWWNNN PIC16F54 -E/SS e3 0720CBP 28-Lead PDIP Example XXXXXXXXXXXXXXX XXXXXXXXXXXXXXX XXXXXXXXXXXXXXX YYWWNNN >h Legend: XX...
PIC16F5X Package Marking Information (Continued) 28-Lead SOIC XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX YYWWNNN 28-Lead SSOP XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN 28-Lead SPDIP (.300") XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN >h Example PIC16F57 -E/SO e3 0718CDK Example PIC16F57 -E/SS e3 0725CBK Example PIC16F57 -I/P e3 0717HAT >h 40-Lead PDIP (.
PIC16F5X 18-Lead Plastic Dual In-Line (P) – 300 mil Body [PDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging N NOTE 1 E1 1 2 3 D E A2 A L c A1 b1 b e eB Units Dimension Limits Number of Pins INCHES MIN N NOM MAX 18 Pitch e Top to Seating Plane A – – .210 Molded Package Thickness A2 .115 .130 .195 Base to Seating Plane A1 .015 – – Shoulder to Shoulder Width E .300 .310 .
PIC16F5X 18-Lead Plastic Small Outline (SO) – Wide, 7.50 mm Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D N E E1 NOTE 1 1 2 3 b e α h h c φ A2 A A1 β L L1 Units Dimension Limits Number of Pins MILLIMETERS MIN N NOM MAX 18 Pitch e Overall Height A – 1.27 BSC – Molded Package Thickness A2 2.05 – – Standoff § A1 0.10 – 0.30 Overall Width E Molded Package Width E1 7.
PIC16F5X 20-Lead Plastic Shrink Small Outline (SS) – 5.30 mm Body [SSOP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D N E E1 NOTE 1 1 2 b e c A2 A φ A1 L1 Units Dimension Limits Number of Pins L MILLIMETERS MIN N NOM MAX 20 Pitch e Overall Height A – 0.65 BSC – 2.00 Molded Package Thickness A2 1.65 1.75 1.85 Standoff A1 0.05 – – Overall Width E 7.40 7.80 8.
PIC16F5X 28-Lead Skinny Plastic Dual In-Line (SP) – 300 mil Body [SPDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging N NOTE 1 E1 1 2 3 D E A2 A L c b1 A1 b e eB Units Dimension Limits Number of Pins INCHES MIN N NOM MAX 28 Pitch e Top to Seating Plane A – – .200 Molded Package Thickness A2 .120 .135 .150 Base to Seating Plane A1 .015 – – Shoulder to Shoulder Width E .290 .
PIC16F5X 28-Lead Plastic Dual In-Line (P) – 600 mil Body [PDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging N E1 NOTE 1 1 2 3 D E A2 A L c b1 A1 b e eB Units Dimension Limits Number of Pins INCHES MIN N NOM MAX 28 Pitch e Top to Seating Plane A – – .250 Molded Package Thickness A2 .125 – .195 Base to Seating Plane A1 .015 – – Shoulder to Shoulder Width E .590 – .
PIC16F5X 28-Lead Plastic Small Outline (SO) – Wide, 7.50 mm Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D N E E1 NOTE 1 1 2 3 b e h α A2 A h c φ L A1 L1 Units Dimension Limits Number of Pins β MILLIMETERS MIN N NOM MAX 28 Pitch e Overall Height A – 1.27 BSC – Molded Package Thickness A2 2.05 – – Standoff § A1 0.10 – 0.30 Overall Width E Molded Package Width E1 7.
PIC16F5X 28-Lead Plastic Shrink Small Outline (SS) – 5.30 mm Body [SSOP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D N E E1 1 2 NOTE 1 b e c A2 A φ A1 L L1 Units Dimension Limits Number of Pins MILLIMETERS MIN N NOM MAX 28 Pitch e Overall Height A – 0.65 BSC – 2.00 Molded Package Thickness A2 1.65 1.75 1.85 Standoff A1 0.05 – – Overall Width E 7.40 7.80 8.
PIC16F5X 40-Lead Plastic Dual In-Line (P) – 600 mil Body [PDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging N NOTE 1 E1 1 2 3 D E A2 A L c b1 A1 b e eB Units Dimension Limits Number of Pins INCHES MIN N NOM MAX 40 Pitch e Top to Seating Plane A – – .250 Molded Package Thickness A2 .125 – .195 Base to Seating Plane A1 .015 – – Shoulder to Shoulder Width E .590 – .
PIC16F5X 44-Lead Plastic Thin Quad Flatpack (PT) – 10x10x1 mm Body, 2.00 mm Footprint [TQFP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D D1 E e E1 N b NOTE 1 1 2 3 NOTE 2 α A c φ β L A1 Units Dimension Limits Number of Leads A2 L1 MILLIMETERS MIN N NOM MAX 44 Lead Pitch e Overall Height A – 0.80 BSC – Molded Package Thickness A2 0.95 1.00 1.05 Standoff A1 0.05 – 0.
PIC16F5X APPENDIX A: DATA SHEET REVISION HISTORY Revision D (04/2007) Changed PICmicro to PIC; Replaced Dev. Tool Section; Updated Package Marking Information and replaced Package Drawings (Rev. AP) DS41213D-page 80 © 2007 Microchip Technology Inc.
PIC16F5X A G Absolute Maximum Ratings PIC1654/57 ................................................................. 57 PIC1659 ...................................................................... 58 ADDWF ............................................................................... 43 ALU ....................................................................................... 7 ANDLW ............................................................................... 43 ANDWF ................................
PIC16F5X PD bit ............................................................................ 17, 23 PICSTART Plus Development Programmer ....................... 56 Pinout Description - PIC16F54.............................................. 9 Pinout Description - PIC16F57............................................ 10 Pinout Description - PIC16F59............................................ 11 PORTA................................................................................ 29 Value on Reset ............
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PIC16F5X PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX XXX Device Temperature Range Package Pattern Examples: a) b) c) Device PIC16F54 – VDD PIC16F54T(1) – VDD PIC16F57 – VDD PIC16F57T(1) – VDD range 2.0V to 5.5V range 2.0V to 5.5V range 2.0V to 5.5V range 2.0V to 5.
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