Datasheet

PIC16F57
DS41208C-page 4 Preliminary © 2007 Microchip Technology Inc.
2.4.3.1 Load Data For Program Memory
After receiving this command, the chip will load in a
14-bit “data word” when 16 cycles are applied, as
described previously. Because this is a 12-bit core, the
two MSbs of the data word are ignored. A timing
diagram for the Load Data command is shown in
Figure 2-3.
FIGURE 2-3: LOAD DATA COMMAND (PROGRAM/VERIFY)
2.4.3.2 Read Data From Program Memory
After receiving this command, the chip will transmit
data bits out of the program memory (user or
configuration) currently addressed, starting with the
second rising edge of the clock input. The data pin will
go into Output mode on the second rising clock edge,
and it will revert to Input mode (high-impedance) after
the 16th rising edge. Because this is a 12-bit core, the
two MSbs of the 14-bit word will be read as ‘1’s.
If the program memory is code-protected (CP
= 0),
portions of the program memory will be read as zeros.
See Section 4.0 “Code Protection” for details.
FIGURE 2-4: READ DATA FROM PROGRAM MEMORY COMMAND
TDLY2
15
5432
1
6
5
43
T
HLD1
1
T
SET1
21
ICSPCLK
0
ICSPDAT
00
TDLY1
xx strt_bit
LSb MSb stp_bit
TSET1
-+T
HLD1
16
TDLY1
T
SET1
T
HLD1
T
DLY2
12 3 4 56
1
0
1
0
x
x
12 3 4 5 15
16
TDLY3
Input
Output
Input
strt_bit
stp_bit
LSb
MSb
0
ICSPCLK
ICSPDAT