Datasheet

© 2007 Microchip Technology Inc. Preliminary DS41208C-page 13
PIC16F57
5.0 PROGRAM/VERIFY MODE ELECTRICAL CHARACTERISTICS
TABLE 5-1: AC/DC CHARACTERISTICS TIMING REQUIREMENTS FOR PROGRAM/VERIFY
MODE
AC/DC CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Operating Temperature 10°C TA 40°C
Operating Voltage 4.5V V
DD 5.5V
Sym. Characteristics Min. Typ. Max. Units Conditions/Comments
General
V
DDPROG VDD level for programming operations,
program memory
4.5 5.5 V
V
DDERA VDD level for Bulk Erase operations,
program memory
4.5 5.5 V
I
DDPROG IDD level for programming operations,
program memory
——0.5mA
I
DDERA IDD level for Bulk Erase operations,
program memory
——0.5mA
V
PP High voltage on MCLR for Program/Verify
mode entry
12.5 13.5 V
I
PP MCLR pin current during Program/Verify
mode
0.45 mA
T
VHHR MCLR rise time (VSS to VIHH) for Program/
Verify mode entry
——1.0μs
T
PPDP Hold time after VPP 5—μs
VIH1 (ICSPCLK, ICSPDAT) input high level 0.8 VDD ——V
V
IL1 (ICSPCLK, ICSPDAT) input low level 0.2 VDD V
TSET0 ICSPCLK, ICSPDAT setup time before
MCLR
(Program/Verify mode selection
pattern setup time)
100 ns
T
HLD0 ICSPCLK, ICSPDAT hold time after
MCLR
(Program/Verify mode selection
pattern setup time)
5—μs
Serial Program/Verify
T
SET1 Data in setup time before clock 100 ns
THLD1 Data in hold time after clock 100 ns
T
DLY1 Data input not driven to next clock input
(delay required between command/data or
command/command)
1.0 μs
TDLY2 Delay between clockto clockof next
command or data
1.0 μs
T
DLY3 Clock to data out valid (during Read Data) 80 ns
T
ERA Erase cycle time 10
(1)
ms
TPROG Programming cycle time (externally timed) 2
(1)
ms
T
DIS Time delay for internal programming
voltage discharge
100 μs
T
RESET Time between exiting Program mode with
V
DD and VPP at GND and then re-entering
Program mode by applying V
DD
—10ms
Note 1: Minimum time to ensure that function completes successfully over voltage, temperature and device variations.