Datasheet

PIC16F527
DS41652A-page 72 Preliminary  2012 Microchip Technology Inc.
REGISTER 12-1: OPACON: OP AMP CONTROL REGISTER
12.2 Effects of a Reset
A device Reset forces all registers to their Reset state.
This disables both op amps.
12.3 OPA Module Performance
Common AC and DC performance specifications for
the OPA module:
• Common Mode Voltage Range
• Leakage Current
• Input Offset Voltage
• Open Loop Gain
• Gain Bandwidth Product (GBWP)
Common mode voltage range is the specified voltage
range for the OPA+ and OPA- inputs, for which the OPA
module will perform to within its specifications. The
OPA module is designed to operate with input voltages
between 0 and V
DD-1.5V. Behavior for common mode
voltages greater than V
DD-1.5V, or below 0V, are
beyond the normal operating range.
Leakage current is a measure of the small source or
sink currents on the OPA+ and OPA- inputs. To mini-
mize the effect of leakage currents, the effective imped-
ances connected to the OPA+ and OPA- inputs should
be kept as small as possible and equal.
Input offset voltage is a measure of the voltage differ-
ence between the OPA+ and OPA- inputs in a closed
loop circuit with the OPA in its linear region. The offset
voltage will appear as a DC offset in the output equal to
the input offset voltage, multiplied by the gain of the
circuit. The input offset voltage is also affected by the
common mode voltage.
Open loop gain is the ratio of the output voltage to the
differential input voltage, (OPA+) - (OPA-). The gain is
greatest at DC and falls off with frequency.
Gain Bandwidth Product or GBWP is the frequency
at which the open loop gain falls off to 0 dB.
12.4 Effects of Sleep
When enabled, the op amps continue to operate and
consume current while the processor is in Sleep mode.
TABLE 12-1: REGISTERS ASSOCIATED WITH THE OPA MODULE
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0
— — — — — — OPA2ON OPA1ON
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-2 Unimplemented: Read as ‘0’
bit 1 OPA2ON: Op Amp Enable bit
1 = Op amp 2 is enabled
0 = Op amp 2 is disabled
bit 0 OPA1ON: Op Amp Enable bit
1 = Op amp 1 is enabled
0 = Op amp 1 is disabled
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Register on
page
ANSEL ANS7 ANS6
ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 32
OPACON
— — — — — —OPA2ONOPA1ON 72
TRIS I/O Control Registers (TRISA, TRISB, TRISC) —
Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used for the OPA
module.