Datasheet

PIC16F527
DS41652A-page 60 Preliminary  2012 Microchip Technology Inc.
9.1.5 SLEEP
This ADC does not have a dedicated ADC clock, and
therefore, no conversion in Sleep is possible. If a
conversion is underway and a Sleep command is
executed, the GO/DONE
and ADON bit will be cleared.
This will stop any conversion in process and power-
down the ADC module to conserve power. Due to the
nature of the conversion process, the ADRES may con-
tain a partial conversion. At least one bit must have
been converted prior to Sleep to have partial conver-
sion data in ADRES. The ADCS and CHS bits are reset
to their default condition; ANS<7:0> = 1s and
CHS<3:0> = 1s.
• For accurate conversions, T
AD must meet the
following:
•500ns < T
AD < 50 s
•TAD = 1/(FOSC/divisor)
Shaded areas indicate T
AD out of range for accurate
conversions. If analog input is desired at these
frequencies, use INTOSC/8 for the ADC clock source.
TABLE 9-2: TAD FOR ADCS SETTINGS WITH VARIOUS OSCILLATORS
TABLE 9-3: EFFECTS OF SLEEP ON ADCON0
Source
ADCS
<1:0>
Divisor
20
MHz
16
MHz
8MHz 4MHz 1MHz
500
kHz
350
kHz
200
kHz
100
kHz
32 kHz
INTOSC 11 4
— —.5s1s — — — — — —
FOSC 10 4
.2 s .25 s.5s1s4s8s11s20s40s 125 s
FOSC 01 8 .4 s.5s1s2s8s16s23s40s 80 s 250 s
FOSC 00 16 .8 s1s2s4s16s32s46s 80 s 160 s 500 s
ANS<7:0> ADCS1 ADCS0 CHS<3:0> GO/DONE
ADON
Entering Sleep Unchanged 11 1 0 0
Wake or Reset 111100