Datasheet

 2012 Microchip Technology Inc. Preliminary DS41652A-page 51
PIC16F527
FIGURE 8-11: WATCHDOG TIMER BLOCK DIAGRAM
TABLE 8-5: REGISTERS ASSOCIATED WITH THE WATCHDOG TIMER
8.8 Time-out Sequence (TO) and
Power-down (PD
) Reset Status
The TO and PD bits in the STATUS register can be
tested to determine if a Reset condition has been
caused by a power-up condition, a MCLR
or Watchdog
Timer (WDT) Reset.
TABLE 8-6: TO/PD STATUS AFTER RESET
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Register on
page
OPTION
RAWU
RAPU
T0SC T0SE PSA PS2 PS1 PS0
20
Legend: Shaded boxes = Not used by Watchdog Timer.
(Figure 7-1)
Postscaler
Note 1: PSA, PS<2:0> are bits in the OPTION register.
WDT Time-out
Watchdog
Time
From Timer0 Clock Source
WDT Enable
Configuration
Bit
PSA
Postscaler
8-to-1 MUX
PS<2:0>
(1)
(Figure 7-4)
To Timer0
0
1
M
U
X
1
0
PSA
(1)
MUX
TO PD Reset Caused By
00WDT wake-up from Sleep
0uWDT time-out (not from Sleep)
10MCLR wake-up from Sleep
11Power-up or Brown-out Reset
uuMCLR
not during Sleep
Legend: u = unchanged
Note 1: The TO and PD bits maintain their status
(u) until a Reset occurs. A low pulse on
the MCLR
input does not change the TO
and PD
Status bits.