Datasheet

PIC16F527
DS41652A-page 36 Preliminary  2012 Microchip Technology Inc.
FIGURE 7-2: TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALE
FIGURE 7-3: TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2
TABLE 7-1: REGISTERS ASSOCIATED WITH TIMER0
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Register
on page
TMR0 Timer0 module Register —
CM1CON0 C1OUT C1OUTEN
C1POL C1T0CS C1ON C1NREF C1PREF C1WU
66
CM2CON0 C2OUT C2OUTEN C2POL C2PREF2 C2ON C2NREF C2PREF1 C2WU
67
OPTION
RAWU RAPU T0CS T0SE PSA PS2 PS1 PS0 20
TRIS
(1)
I/O Control Registers (TRISA, TRISB, TRISC)
—
Legend: Shaded cells are not used by Timer0. – = unimplemented, x = unknown, u = unchanged.
Note 1: The TRIS of the T0CKI pin is overridden when T0CS = 1.
PC – 1
Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Instruction
Fetch
Timer0
PC PC + 1 PC + 2 PC + 3 PC + 4 PC + 6
T0
T0 + 1 T0 + 2 NT0
NT0 + 1
NT0 + 2
MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
Write TMR0
executed
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0 + 1
Read TMR0
reads NT0 + 2
Instruction
Executed
PC + 5
PC
(Program
Counter)
PC – 1
Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Instruction
Fetch
Timer0
PC PC + 1 PC + 2 PC + 3 PC + 4 PC + 6
T0
T0 + 1 NT0
NT0 + 1
MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
Write TMR0
executed
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0 + 1
Read TMR0
reads NT0 + 2
Instruction
Executed
PC + 5
PC
(Program
Counter)