Datasheet

PIC16F527
DS41652A-page 22 Preliminary  2012 Microchip Technology Inc.
4.6 Program Counter
As a program instruction is executed, the Program
Counter (PC) will contain the address of the next
program instruction to be executed. The PC value is
increased by one every instruction cycle, unless an
instruction changes the PC.
For a GOTO instruction, bits <8:0> of the PC are
provided by the GOTO instruction word. The Program
Counter (PCL) is mapped to PC<7:0>. Bit 5 of the
STATUS register provides page information to bit 9 of
the PC (Figure 4-3).
For a CALL instruction, or any instruction where the
PCL is the destination, bits <7:0> of the PC again are
provided by the instruction word. However, PC<8>
does not come from the instruction word, but is always
cleared (Figure 4-3).
Instructions where the PCL is the destination, or modify
PCL instructions, include MOVWF PCL, ADDWF PCL
and BSF PCL,5.
FIGURE 4-3: LOADING OF PC
BRANCH INSTRUCTIONS
4.6.1 EFFECTS OF RESET
The PC is set upon a Reset, which means that the PC
addresses the last location in the last page (i.e., the
oscillator calibration instruction). After executing
MOVLW XX, the PC will roll over to location 00h and
begin executing user code.
The STATUS register page preselect bits are cleared
upon a Reset, which means that page 0 is pre-selected.
Therefore, upon a Reset, a GOTO instruction will
automatically cause the program to jump to page 0 until
the value of the page bits is altered.
4.7 Stack
The PIC16F527 device has a 4-deep, 12-bit wide
hardware PUSH/POP stack.
A CALL instruction or an interrupt will PUSH the current
PC value, incremented by one, into Stack Level 1. If there
was a previous value in the Stack 1 location, it will be
pushed into the Stack 2 location. This process will be
continued throughout the remaining stack locations pop-
ulated with values. If more than four sequential CALLs
are executed, only the most recent four return addresses
are stored.
A RETLW, RETURN or RETFIE instruction will POP
the contents of Stack Level 1 into the PC. If there was
a previous value in the Stack 2 location, it will be copied
into the Stack Level 1 location. This process will be con-
tinued throughout the remaining stack locations popu-
lated with values. If more than four sequential RETLWs
are executed, the stack will be filled with the address
previously stored in Stack Level 4. Note that the
W register will be loaded with the literal value specified
in the instruction. This is particularly useful for the
implementation of data look-up tables within the pro-
gram memory.
Note: Because bit 8 of the PC is cleared in the
CALL instruction or any modify PCL
instruction, all subroutine calls or com-
puted jumps are limited to the first 256
locations of any program memory page
(512 words long).
PA0
Status
PC
87 0
PCL
910
Instruction Word
7 0
GOTO Instruction
CALL or Modify PCL Instruction
PA0
Status
PC
87 0
PCL
910
Instruction Word
7 0
Reset to ‘0’
Note 1: There are no Status bits to indicate Stack
Overflows or Stack Underflow conditions.
2: There are no instruction mnemonics
called PUSH or POP. These are actions
that occur from the execution of the
CALL, RETURN, RETFIE and RETLW
instructions.