PIC16F527 20-Pin, 8-Bit Flash Microcontroller Processor Features: Microcontroller Features: • Interrupt Capability • PIC16F527 Operating Speed: - DC – 20 MHz Crystal oscillator - DC – 200 ns Instruction cycle • Flash Program Memory: - 1024 x 12 user execution memory - 64 x 8 self-writable data memory - 10K minimum erase/write cycles • General Purpose Registers (SRAM): - 68 x 8 for PIC16F527 • Only 36 Single-Word Instructions to Learn: - Added RETURN and RETFIE instructions - Added MOVLB instruction • All
PIC16F527 Program Memory Data Memory Device I/O Flash (words) SRAM (bytes) PIC16F527 1024 FIGURE 1: Comparators Timers 8-bit Flash (bytes) 68 64 18 2 1 8-bit A/D Channels Op Amps 8 2 20-PIN PDIP, SOIC, SSOP DIAGRAM FOR PIC16F527 20-pin PDIP, SSOP, SOIC FIGURE 2: 1 2 RA4 3 RA3/MCLR/VPP RC5 4 5 RC4 6 RC3 7 RC6 8 13 RC7 RB7 9 12 11 PIC16F527 VDD RA5 20 19 VSS 18 17 RA1/ICSPCLK RA2 RC0 16 15 14 10 RA0/ICSPDAT RC1 RC2 RB4 RB5 RB6 20-PIN QFN DIAGRAM FOR PIC16F527 DS4
PIC16F527 20-PIn PDIP/SOIC/SSOP 20-Pin QFN Analog Oscillator Comparator Reference Timers Op Amp Clock Reference ICSP™ Basic Pull-up Interrupt-on-Change 20-PIN ALLOCATION TABLE I/O TABLE 1: RA0 19 16 AN0 — C1IN+ — — — — ICSPDAT — Y Y RA1 18 15 AN1 — C1IN- CVREF — — — ICSPCLK — Y Y RA2 17 14 AN2 — C1OUT — T0CKI — — — — — — RA3 4 1 — — — — — — — — MCLR VPP Y Y RA4 3 20 AN3 OSC2 — — — — CLKOUT — — Y Y RA5 2 19 — OSC1 — —
PIC16F527 Table of Contents 1.0 General Description..................................................................................................................................................................... 5 2.0 PIC16F527 Device Varieties .................................................................................... .................................................................. 7 3.0 Architectural Overview .................................................................................
PIC16F527 1.0 GENERAL DESCRIPTION 1.1 The PIC16F527 device from Microchip Technology is a low-cost, high-performance, 8-bit, fully-static, Flashbased CMOS microcontroller. It employs a RISC architecture with only 36 single-word/single-cycle instructions. All instructions are single cycle except for program branches, which take two cycles. The PIC16F527 device delivers performance an order of magnitude higher than its competitors in the same price category.
PIC16F527 NOTES: DS41652A-page 6 Preliminary 2012 Microchip Technology Inc.
PIC16F527 2.0 PIC16F527 DEVICE VARIETIES A variety of packaging options are available. Depending on application and production requirements, the proper device option can be selected using the information in this section. When placing orders, please use the PIC16F527 Product Identification System at the back of this data sheet to specify the correct part number. 2.1 Quick Turn Programming (QTP) Devices 2.
PIC16F527 NOTES: DS41652A-page 8 Preliminary 2012 Microchip Technology Inc.
PIC16F527 3.0 ARCHITECTURAL OVERVIEW The high performance of the PIC16F527 device can be attributed to a number of architectural features commonly found in RISC microprocessors. To begin with, the PIC16F527 device uses a Harvard architecture in which program and data are accessed on separate buses. This improves bandwidth over traditional von Neumann architectures where program and data are fetched on the same bus.
PIC16F527 FIGURE 3-1: PIC16F527 BLOCK DIAGRAM 11 Flash 1K x 12 Self-write 64x8 Program Bus STACK2 STACK3 12 STACK4 RAM Addr RA0/ICSPDAT RA1/ICSPCLK RA2 RA3/MCLR/VPP RA4/OSC2/CLKOUT RA5/OSC1/CLKIN 9 PORTB Addr MUX Instruction reg 0-4 Direct Addr 3 PORTA RAM 68 bytes File Registers STACK1 Program Memory 8 Data Bus Program Counter Direct Addr BSR 0-7 5-7 RB4 RB5 RB6 RB7 Indirect Addr FSR reg PORTC STATUS reg 8 3 Brown-out Reset Instruction Decode & Control Device Reset Timer OSC1/C
PIC16F527 TABLE 3-2: PIC16F527 PINOUT DESCRIPTION Name Function Input Type Output Type RA0/AN0/C1IN+/ICSPDAT RA0 TTL CMOS ICSPDAT ST CMOS C1IN+ AN — Comparator 1 input. AN0 AN — ADC channel input. RA1 TTL CMOS RA1/AN1/C1IN-/CVREF/ ICSPCLK Description Bidirectional I/O pin. It can be software programmed for internal weak pull-up and wake-up from Sleep on pin change. ICSP™ mode Schmitt Trigger. Bidirectional I/O pin.
PIC16F527 TABLE 3-2: Name RC1/AN5/C2IN- RC2/AN6/OP2 RC3/AN7/OP1 RC4/C2OUT PIC16F527 PINOUT DESCRIPTION Function Input Type Output Type Description RC1 ST CMOS AN5 AN — ADC channel input. C2IN- AN — Comparator 2 input. RC2 ST CMOS Bidirectional I/O port. AN6 AN — ADC channel input. OP2 — AN Op amp 2 output. RC3 ST CMOS Bidirectional I/O port. Bidirectional I/O port. AN7 AN — ADC channel input. OP1 — AN Op amp 1 output. RC4 ST CMOS Bidirectional I/O port.
PIC16F527 3.1 Clocking Scheme/Instruction Cycle 3.2 Instruction Flow/Pipelining An instruction cycle consists of four Q cycles (Q1, Q2, Q3 and Q4). The instruction fetch and execute are pipelined such that fetch takes one instruction cycle, while decode and execute take another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the PC to change (e.g.
PIC16F527 NOTES: DS41652A-page 14 Preliminary 2012 Microchip Technology Inc.
PIC16F527 MEMORY ORGANIZATION FIGURE 4-1: 4.1 Program Memory Organization for PIC16F527 The PIC16F527 device has an 11-bit Program Counter (PC) capable of addressing a 2K x 12 program memory space. Program memory is partitioned into user memory, data memory and configuration memory spaces. The user memory space is the on-chip user program memory.
PIC16F527 4.2 4.2.1 Data Memory (SRAM and FSRs) Data memory is composed of registers or bytes of SRAM. Therefore, data memory for a device is specified by its register file. The register file is divided into two functional groups: Special Function Registers (SFR) and General Purpose Registers (GPR). The General Purpose Register file is accessed directly or indirectly. See Section 4.8 “Direct and Indirect Addressing”. 4.2.
PIC16F527 TABLE 4-1: Address SPECIAL FUNCTION REGISTER SUMMARY Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR/BOR Value on all other Resets Bank 0 N/A W(2) Working Register (W) xxxx xxxx xxxx xxxx N/A TRIS I/O Control Registers (TRISA, TRISB, TRISC) 1111 1111 1111 1111 N/A OPTION Contains control bits to configure Timer0 and Timer0/WDT prescaler 1111 1111 1111 1111 N/A BSR(2) ---- -000 ---- -0uu — — — — — BSR2 BSR1 BSR0 00h INDF Uses contents of F
PIC16F527 TABLE 4-1: Address SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR/BOR Value on all other Resets Bank 2 N/A W(2) Working Register (W) xxxx xxxx xxxx xxxx N/A TRIS I/O Control Registers (TRISA, TRISB, TRISC) 1111 1111 1111 1111 N/A OPTION Contains control bits to configure Timer0 and Timer0/WDT prescaler 1111 1111 1111 1111 N/A BSR(2) ---- -000 ---- -0uu — — — — — BSR2 BSR1 BSR0 40h INDF Uses c
PIC16F527 4.3 STATUS Register This register contains the arithmetic status of the ALU, the Reset status and the page preselect bit. The STATUS register can be the destination for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable.
PIC16F527 4.4 OPTION Register The OPTION register is a 8-bit wide, write-only register, which contains various control bits to configure the Timer0/WDT prescaler and Timer0. Note: By executing the OPTION instruction, the contents of the W register will be transferred to the OPTION register. A Reset sets the OPTION <7:0> bits. REGISTER 4-2: If TRIS bit is set to ‘0’, the wake-up on change and pull-up functions are disabled for that pin (i.e., note that TRIS overrides Option control of RAPU and RAWU).
PIC16F527 4.5 OSCCAL Register The Oscillator Calibration (OSCCAL) register is used to calibrate the 8 MHz internal oscillator macro. It contains seven bits of calibration that uses a two’s complement scheme for controlling the oscillator speed. See Register 4-3 for details.
PIC16F527 4.6 4.6.1 Program Counter EFFECTS OF RESET As a program instruction is executed, the Program Counter (PC) will contain the address of the next program instruction to be executed. The PC value is increased by one every instruction cycle, unless an instruction changes the PC. The PC is set upon a Reset, which means that the PC addresses the last location in the last page (i.e., the oscillator calibration instruction).
PIC16F527 4.8 4.8.1 Direct and Indirect Addressing DIRECT DATA ADDRESSING: BSR REGISTER Traditional data memory addressing is performed in the Direct Addressing mode. In Direct Addressing, the Bank Select Register bits BSR<1:0>, in the new BSR register, are used to select the data memory bank. The address location within that bank comes directly from the opcode being executed.
PIC16F527 FIGURE 4-4: (BSR) 1 DIRECT/INDIRECT ADDRESSING Direct Addressing (opcode) 4 0 bank select 3 2 1 Indirect Addressing (FSR) 0 6 location select 00 01 10 11 5 4 bank select 3 2 1 0 location select 00h Data Memory(1) 0Bh 0Ch Addresses map back to addresses in Bank 0. 0Fh 10h 2Fh 4Fh 6Fh 1Fh 3Fh 5Fh 7Fh Bank 0 Bank 1 Bank 2 Bank 3 Note 1:For register map detail see Section 4.3 “STATUS Register”. DS41652A-page 24 Preliminary 2012 Microchip Technology Inc.
PIC16F527 5.0 FLASH DATA MEMORY CONTROL 3. 4. The Flash data memory is readable and writable during normal operation (full VDD range). This memory is not directly mapped in the register file space. Instead, it is indirectly addressed through the Special Function Registers (SFRs). 5.
PIC16F527 5.2.2 WRITING TO FLASH DATA MEMORY 5.3 Once a cell is erased, new data can be written. Program execution is suspended during the write cycle. The following sequence must be performed for a single byte write. 1. 2. 3. 4. Load EEADR with the address. Load EEDATA with the data to write. Set the WREN bit to enable write access to the array. Set the WR bit to initiate the erase cycle.
PIC16F527 5.
PIC16F527 REGISTER 5-3: EECON: FLASH CONTROL REGISTER U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — FREE WRERR WREN WR RD bit 7 bit 0 Legend: S = Bit can only be set R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’.
PIC16F527 6.0 I/O PORT 6.2 As with any other register, the I/O register(s) can be written and read under program control. However, read instructions (e.g., MOVF PORTB,W) always read the I/O pins independent of the pin’s Input/Output modes. On Reset, all I/O ports are defined as input (inputs are at highimpedance) since the I/O control registers are all set. 6.1 PORTA 2012 Microchip Technology Inc. PORTB is a 4-bit I/O register. Only the high-order four bits are used (RB<7:4>).
PIC16F527 6.5 FIGURE 6-1: I/O Interfacing The equivalent circuit for an I/O port pin is shown in Figure 6-1. All port pins, except the MCLR pin which is input-only, may be used for both input and output operations. For input operations, these ports are non-latching. Any input must be present until read by an input instruction (e.g., MOVF PORTB, W). The outputs are latched and remain unchanged until the output latch is rewritten.
PIC16F527 6.6 Register Definitions — PORT Control REGISTER 6-1: PORTA: PORTA REGISTER U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — — RA5 RA4 RA3 RA2 RA1 RA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RA<5:0>: PORTA I/O Pin bits 1 = Port pin is >VIH min. 0 = Port pin is
PIC16F527 REGISTER 6-3: PORTC: PORTC REGISTER R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 x = Bit is unknown RC<7:0>: PORTC I/O Pin bits 1 = Port pin is >VIH min. 0 = Port pin is
PIC16F527 6.7 EXAMPLE 6-1: I/O Programming Considerations 6.7.1 BIDIRECTIONAL I/O PORTS Some instructions operate internally as read followed by write operations. The BCF and BSF instructions, for example, read the entire port into the CPU, execute the bit operation and rewrite the result. Caution must be used when these instructions are applied to a port where one or more pins are used as input/outputs.
PIC16F527 NOTES: DS41652A-page 34 Preliminary 2012 Microchip Technology Inc.
PIC16F527 7.0 TIMER0 MODULE AND TMR0 REGISTER There are two types of Counter mode. The first Counter mode uses the T0CKI pin to increment Timer0. It is selected by setting the T0CS bit of the OPTION register, setting the C1T0CS bit of the CM1CON0 register and setting the C1OUTEN bit of the CM1CON0 register. In this mode, Timer0 will increment either on every rising or falling edge of pin T0CKI. The T0SE bit of the OPTION register determines the source edge. Clearing the T0SE bit selects the rising edge.
PIC16F527 FIGURE 7-2: PC (Program Counter) TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC – 1 Instruction Fetch PC PC + 1 MOVWF TMR0 T0 Timer0 T0 + 1 T0 + 2 Instruction Executed Write TMR0 executed FIGURE 7-3: PC (Program Counter) PC + 2 PC + 3 PC + 4 PC + 5 PC + 6 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W NT0 + 1 NT0 Read TMR0 reads NT0 Read TMR0 reads NT0 Read TMR0 reads
PIC16F527 7.1 Using Timer0 with an External Clock When an external clock input is used for Timer0, it must meet certain requirements. The external clock requirement is due to internal phase clock (TOSC) synchronization. Also, there is a delay in the actual incrementing of Timer0 after synchronization. 7.1.1 EXTERNAL CLOCK SYNCHRONIZATION When no prescaler is used, the external clock input is the same as the prescaler output.
PIC16F527 7.2 EXAMPLE 7-1: Prescaler An 8-bit counter is available as a prescaler for the Timer0 module or as a postscaler for the Watchdog Timer (WDT), respectively (see Section 8.7 “Watchdog Timer (WDT)”). For simplicity, this counter is being referred to as “prescaler” throughout this data sheet. Note: The prescaler may be used by either the Timer0 module or the WDT, but not both. Thus, a prescaler assignment for the Timer0 module means that there is no prescaler for the WDT and vice versa.
PIC16F527 FIGURE 7-5: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER TCY (= FOSC/4) Data Bus 0 Comparator Output 0 1 8 M U X 1 0 1 T0CKI Pin M U X T0SE(1) T0CS(1) Sync 2 Cycles TMR0 Reg PSA(1) C1TOCS 0 Watchdog Timer 1 8-bit Prescaler M U X 8 PS<2:0>(1) 8-to-1 MUX (1) PSA WDT Enable bit 1 0 MUX PSA(1) WDT Time-out Note 1: T0CS, T0SE, PSA, PS<2:0> are bits in the OPTION register. 2012 Microchip Technology Inc.
PIC16F527 NOTES: DS41652A-page 40 Preliminary 2012 Microchip Technology Inc.
PIC16F527 8.0 SPECIAL FEATURES OF THE CPU What sets a microcontroller apart from other processors are special circuits that deal with the needs of real-time applications. The PIC16F527 microcontrollers have a host of such features intended to maximize system reliability, minimize cost through elimination of external components, provide powersaving operating modes and offer code protection. These features are: 8.
PIC16F527 8.
PIC16F527 8.3 FIGURE 8-1: Oscillator Configurations 8.3.1 OSCILLATOR TYPES The PIC16F527 device can be operated in up to six different oscillator modes. The user can program up to three Configuration bits (FOSC<2:0>). To select one of these modes: • • • • • • LP: XT: HS: INTRC: EXTRC: EC: 8.3.
PIC16F527 TABLE 8-2: CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR(2) Osc Type Resonator Freq. Cap. Range C1 Cap. Range C2 LP 32 kHz(1) 15 pF 15 pF XT 200 kHz 1 MHz 4 MHz 47-68 pF 15 pF 15 pF 47-68 pF 15 pF 15 pF 20 MHz 15-47 pF 15-47 pF HS Note 1: 2: Figure 8-4 shows a series resonant oscillator circuit. This circuit is also designed to use the fundamental frequency of the crystal. The inverter performs a 180degree phase shift in a series resonant oscillator circuit.
PIC16F527 Also, see the Electrical Specifications section for variation of oscillator frequency due to VDD for given REXT/CEXT values, as well as frequency variation due to operating temperature for given R, C and VDD values. FIGURE 8-5: EXTERNAL RC OSCILLATOR MODE VDD REXT OSC1 Internal clock N CEXT PIC® Device VSS FOSC/4 OSC2/CLKOUT 8.3.5 INTERNAL 4/8 MHz RC OSCILLATOR The internal RC oscillator provides a fixed 4/8 MHz (nominal) system clock at VDD = 5V and 25°C, (see Section 15.
PIC16F527 8.4 Reset The device differentiates between various kinds of Reset: • • • • • • • Power-on Reset (POR) Brown-out Reset (BOR) MCLR Reset during normal operation MCLR Reset during Sleep WDT Time-out Reset during normal operation WDT Time-out Reset during Sleep Wake-up from Sleep on pin change Some registers are not reset in any way, they are unknown on POR/BOR and unchanged in any other Reset.
PIC16F527 8.4.1 MCLR ENABLE This Configuration bit, when set to a ‘1’, enables the external MCLR Reset function. When cleared to ‘0’, the MCLR function is tied to the internal VDD and the pin is assigned to be an input-only pin function. See Figure 8-6. FIGURE 8-6: MCLR SELECT A power-up example where MCLR is held low is shown in Figure 8-8. VDD is allowed to rise and stabilize before bringing MCLR high. The chip will actually come out of Reset TDRT msec after MCLR goes high. RAPU MCLR/VPP MCLRE 8.
PIC16F527 FIGURE 8-7: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT VDD Power-up Detect POR (Power-on Reset) MCLR/VPP MCLR Reset S Q R Q MCLRE WDT Time-out Pin Change Sleep WDT Reset Start-up Timer (10 us or 18 ms) CHIP Reset Wake-up on pin Change Reset Comparator Change Wake-up on Comparator Change TIME-OUT SEQUENCE ON POWER-UP (MCLR PULLED LOW) FIGURE 8-8: VDD MCLR Internal POR TDRT DRT Time-out Internal Reset FIGURE 8-9: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): FAST VDD RI
PIC16F527 FIGURE 8-10: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): SLOW VDD RISE TIME V1 VDD MCLR Internal POR TDRT DRT Time-out Internal Reset Note: When VDD rises slowly, the TDRT time-out expires long before VDD has reached its final value. In this example, the chip will reset properly if, and only if, V1 VDD min. 2012 Microchip Technology Inc.
PIC16F527 8.6 TABLE 8-4: Device Reset Timer (DRT) On the PIC16F527 device, the DRT runs any time the device is powered up. DRT runs from Reset and varies based on oscillator selection and Reset type (see Table 8-4). The DRT operates on an internal RC oscillator. The processor is kept in Reset as long as the DRT is active. The DRT delay allows VDD to rise above VDD min. and for the oscillator to stabilize.
PIC16F527 FIGURE 8-11: WATCHDOG TIMER BLOCK DIAGRAM From Timer0 Clock Source (Figure 7-1) 0 M U X 1 Watchdog Time Postscaler 8-to-1 MUX PS<2:0>(1) PSA WDT Enable Configuration Bit To Timer0 (Figure 7-4) 0 1 MUX PSA(1) WDT Time-out Note 1: TABLE 8-5: PSA, PS<2:0> are bits in the OPTION register.
PIC16F527 8.9 Brown-out Reset (BOR) On any Reset (Power-on, Brown-out Reset, Watchdog Timer, etc.), the chip will remain in Reset until VDD rises above VBOR (see Figure 8-12). If enabled, the Device Reset Timer will now be invoked, and will keep the chip in Reset an additional 18 ms. A brown-out is a condition where device power (VDD) dips below its minimum value, but not to zero, and then recovers. The device should be reset in the event of a brown-out.
PIC16F527 8.10 Power-down Mode (Sleep) A device may be powered down (Sleep) and later powered up (wake-up from Sleep). 8.10.1 The WDT is cleared when the device wakes from Sleep, regardless of the wake-up source. Note: SLEEP The Power-Down mode is entered by executing a SLEEP instruction. If enabled, the Watchdog Timer will be cleared but keeps running, the TO bit of the STATUS register is set, the PD bit of the STATUS register is cleared and the oscillator driver is turned off.
PIC16F527 8.11 Interrupts 8.13 The interrupt feature allows certain events to preempt normal program flow. Firmware is used to determine the source of the interrupt and act accordingly. Some interrupts can be configured to wake the MCU from Sleep mode.
PIC16F527 8.
PIC16F527 REGISTER 8-3: INTCON1 REGISTER R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0 ADIE CWIE T0IE RAIE — — — WUR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ADIE: A/D Converter (ADC) Interrupt Enable bit 1 = Enables the ADC interrupt 0 = Disables the ADC interrupt bit 6 CWIE: Comparator 1 and 2 Interrupt Enable bit 1 = Enables the Comparator 1 and 2 Inte
PIC16F527 8.16 FIGURE 8-14: Program Verification/Code Protection If the code protection bit has not been programmed, the on-chip program memory can be read out for verification purposes. The first 64 locations and the last location (OSCCAL) can be read, regardless of the code protection bit setting. 8.17 External Connector Signals ID Locations Four memory locations are designated as ID locations where the user can store checksum or other code identification numbers.
PIC16F527 NOTES: DS41652A-page 58 Preliminary 2012 Microchip Technology Inc.
PIC16F527 9.0 ANALOG-TO-DIGITAL (A/D) CONVERTER Note: The A/D Converter allows conversion of an analog signal into an 8-bit digital signal. 9.1 Clock Divisors The ADC has four clock source settings ADCS<1:0>. There are three divisor values 16, 8 and 4. The fourth setting is INTOSC with a divisor of four. These settings will allow a proper conversion when using an external oscillator at speeds from 20 MHz to 350 kHz.
PIC16F527 9.1.5 SLEEP This ADC does not have a dedicated ADC clock, and therefore, no conversion in Sleep is possible. If a conversion is underway and a Sleep command is executed, the GO/DONE and ADON bit will be cleared. This will stop any conversion in process and powerdown the ADC module to conserve power. Due to the nature of the conversion process, the ADRES may contain a partial conversion. At least one bit must have been converted prior to Sleep to have partial conversion data in ADRES.
PIC16F527 9.1.6 ANALOG CONVERSION RESULT REGISTER right shifts of the ‘leading one’ have taken place, the conversion is complete; the ‘leading one’ has been shifted out and the GO/DONE bit is cleared. The ADRES register contains the results of the last conversion. These results are present during the sampling period of the next analog conversion process. After the sampling period is over, ADRES is cleared (= 0).
PIC16F527 REGISTER 9-2: ADRES: A/D CONVERSION RESULTS REGISTER R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X ADRES7 ADRES6 ADRES5 ADRES4 ADRES3 ADRES2 ADRES1 ADRES0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 ADRES<7:0>: ADC Result Register bits EXAMPLE 9-1: PERFORMING AN ANALOG-TO-DIGITAL CONVERSION EXAMPLE 9-2: ;Sample code operates out of BANK0 loop0 x = Bit is u
PIC16F527 10.0 COMPARATOR(S) This device contains two comparators comparator voltage reference. FIGURE 10-1: and a COMPARATORS BLOCK DIAGRAM RA2/C1OUT C1PREF C1IN+ 1 C1OUTEN + C1IN- 0 C1OUT (Register) 1 - VREF (0.6V) 0 C1NREF C1POL C1ON 0 T0CKI 1 T0CKI Pin C1T0CS Q D S RC4/C2OUT C2PREF1 C2IN+ READ CM1CON0 C2OUTEN 1 + 0 1 C2OUT (Register) 0 C2PREF2 C2IN- C2POL C2ON 1 0 CVREF C2NREF Q D C1WU S CWIF READ CM2CON0 C2WU 2012 Microchip Technology Inc.
PIC16F527 10.1 Comparator Operation 10.4 A single comparator is shown in Figure 10-2 along with the relationship between the analog input levels and the digital output. When the analog input at VIN+ is less than the analog input VIN-, the output of the comparator is a digital low level. The shaded area of the output of the comparator in Figure 10-2 represent the uncertainty due to input offsets and response time. See Table 15-2 for Common Mode Voltage. FIGURE 10-2: VIN+ Note: 10.
PIC16F527 FIGURE 10-3: ANALOG INPUT MODE VDD VT = 0.6V RS < 10 K RIC AIN CPIN 5 pF VA VT = 0.6V ILEAKAGE ±500 nA VSS Legend: CPIN VT ILEAKAGE RIC RS VA 2012 Microchip Technology Inc.
PIC16F527 10.
PIC16F527 REGISTER 10-2: CM2CON0: COMPARATOR C2 CONTROL REGISTER R-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 C2OUT C2OUTEN C2POL C2PREF2 C2ON C2NREF C2PREF1 C2WU bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 C2OUT: Comparator Output bit 1 = VIN+ > VIN0 = VIN+ < VIN- bit 6 C2OUTEN: Comparator Output Enable bit(1), (2) 1 = Output of comparator is NOT placed on the C2OUT pin 0
PIC16F527 NOTES: DS41652A-page 68 Preliminary 2012 Microchip Technology Inc.
PIC16F527 11.0 COMPARATOR VOLTAGE REFERENCE MODULE 11.2 The Comparator Voltage Reference module also allows the selection of an internally generated voltage reference for one of the C2 comparator inputs. The VRCON register (Register 11-1) controls the voltage reference module shown in Figure 11-1. 11.1 Configuring The Voltage Reference The voltage reference can output 32 voltage levels; 16 in a high range and 16 in a low range.
PIC16F527 FIGURE 11-1: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM 16 Stages 8R R R R R VDD 8R VRR 16-1 Analog MUX VREN CVREF to Comparator 2 Input VR<3:0> RA1/CVREF VREN VR<3:0> = 0000 VRR VROE TABLE 11-1: REGISTERS ASSOCIATED WITH COMPARATOR VOLTAGE REFERENCE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on page VREN VROE VRR — VR3 VR2 VR1 VR0 69 CM1CON0 C1OUT C1OUTEN C1POL C1T0CS C1ON C1NREF C1PREF C1WU 66 CM2CON0 C2OUT C2OUTEN C2POL C2PREF2 C2ON
PIC16F527 12.0 OPERATIONAL AMPLIFIER (OPA) MODULE The OPA module has the following features: • Two independent Operational Amplifiers • External connections to all ports • 3 MHz Gain Bandwidth Product (GBWP) 12.1 OPACON Register The OPA module is enabled by setting the OPAxON bit of the OPACON Register. When enabled, OPAxON forces the output driver of OP1 for OPA1, and OP2 for OPA2, into tri-state to prevent contention between the driver and the OPA output.
PIC16F527 REGISTER 12-1: OPACON: OP AMP CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — — — OPA2ON OPA1ON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-2 Unimplemented: Read as ‘0’ bit 1 OPA2ON: Op Amp Enable bit 1 = Op amp 2 is enabled 0 = Op amp 2 is disabled bit 0 OPA1ON: Op Amp Enable bit 1 = Op amp 1 is enabled 0 = Op amp 1 is disabled 12.
PIC16F527 13.0 INSTRUCTION SET SUMMARY The PIC16 instruction set is highly orthogonal and is comprised of three basic categories. • Byte-oriented operations • Bit-oriented operations • Literal and control operations Each PIC16 instruction is a 12-bit word divided into an opcode, which specifies the instruction type, and one or more operands which further specify the operation of the instruction.
PIC16F527 TABLE 13-2: Mnemonic, Operands ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF INSTRUCTION SET SUMMARY 12-Bit Opcode Description Cycles MSb LSb Status Notes Affected f, d f, d f — f, d f, d f, d f, d f, d f, d f, d f — f, d f, d f, d f, d f, d 0001 11df ffff C, DC, Z 1, 2, 4 Add W and f 1 0001 01df ffff AND W with f 1 Z 2, 4 0000 011f ffff Clear f 1 Z 4 0000 0100 0000 Clear W 1 Z 0010 01df ffff Complement f 1 Z 0000 11df ffff Decrement f 1 Z
PIC16F527 ADDWF Add W and f BCF f,d Bit Clear f Syntax: [ label ] ADDWF Syntax: [ label ] BCF Operands: 0 f 31 d 01 Operands: 0 f 31 0b7 Operation: (W) + (f) (dest) Operation: 0 (f) Status Affected: C, DC, Z Status Affected: None Description: Bit ‘b’ in register ‘f’ is cleared. Description: Add the contents of the W register and register ‘f’. If ‘d’ is’0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’.
PIC16F527 BTFSS Bit Test f, Skip if Set CLRW Syntax: [ label ] BTFSS f,b Syntax: [ label ] CLRW 0 f 31 0b<7 Operands: None Operation: 00h (W); 1Z Operands: Clear W Operation: skip if (f) = 1 Status Affected: None Status Affected: Z Description: If bit ‘b’ in register ‘f’ is ‘1’, then the next instruction is skipped.
PIC16F527 DECF Decrement f INCF Syntax: [ label ] DECF f,d Syntax: [ label ] Operands: 0 f 31 d [0,1] Operands: 0 f 31 d [0,1] Operation: (f) – 1 (dest) Operation: (f) + 1 (dest) Status Affected: Z Status Affected: Z Description: Decrement register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. Description: The contents of register ‘f’ are incremented.
PIC16F527 IORWF Inclusive OR W with f MOVWF Syntax: [ label ] Syntax: [ label ] Operands: 0 f 31 d [0,1] Operands: 0 f 31 Operation: (W).OR. (f) (dest) (W) (f) Operation: Status Affected: None Status Affected: Z Description: Description: Inclusive OR the W register with register ‘f’. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is placed back in register ‘f’. Move data from the W register to register ‘f’.
PIC16F527 RETLW Return with Literal in W RRF Syntax: [ label ] Syntax: [ label ] Operands: 0 k 255 Operands: Operation: k (W); TOS PC 0 f 31 d [0,1] Operation: See description below Status Affected: None Status Affected: C Description: The W register is loaded with the eight-bit literal ‘k’. The program counter is loaded from the top of the stack (the return address). This is a two-cycle instruction.
PIC16F527 SWAPF Swap Nibbles in f XORWF Exclusive OR W with f Syntax: [ label ] SWAPF f,d Syntax: [ label ] XORWF Operands: 0 f 31 d [0,1] Operands: 0 f 31 d [0,1] Operation: (f<3:0>) (dest<7:4>); (f<7:4>) (dest<3:0>) Operation: (W) .XOR. (f) dest) Status Affected: Z Status Affected: None Description: Description: The upper and lower nibbles of register ‘f’ are exchanged. If ‘d’ is ‘0’, the result is placed in W register.
PIC16F527 14.0 DEVELOPMENT SUPPORT 14.
PIC16F527 14.2 MPLAB C Compilers for Various Device Families The MPLAB C Compiler code development systems are complete ANSI C compilers for Microchip’s PIC18, PIC24 and PIC32 families of microcontrollers and the dsPIC30 and dsPIC33 families of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. 14.
PIC16F527 14.7 MPLAB SIM Software Simulator 14.9 The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC® DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis.
PIC16F527 14.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express 14.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits The PICkit™ 2 Development Programmer/Debugger is a low-cost development tool with an easy to use interface for programming and debugging Microchip’s Flash families of microcontrollers.
PIC16F527 15.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings(†) Ambient temperature under bias.......................................................................................................... -40°C to +125°C Storage temperature ............................................................................................................................ -65°C to +150°C Voltage on VDD with respect to VSS ...........................................................................................
PIC16F527 PIC16F527 VOLTAGE-FREQUENCY GRAPH, -40C TA +125C FIGURE 15-1: 6.0 5.5 5.0 VDD (Volts) 4.5 4.0 3.5 3.0 2.5 2.0 0 4 8 20 10 25 Frequency (MHz) FIGURE 15-2: MAXIMUM OSCILLATOR FREQUENCY TABLE Oscillator Mode LP XT XTRC INTOSC EC HS 0 200 kHz 4 MHz 8 MHz 20 MHz Frequency DS41652A-page 86 Preliminary 2012 Microchip Technology Inc.
PIC16F527 15.1 DC Characteristics: PIC16F527 (Industrial) Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +85C (industrial) DC Characteristics Param No. D001 Sym. VDD Characteristic Supply Voltage Voltage(2) D002 VDR RAM Data Retention D003 VPOR VDD Start Voltage to ensure Power-on Reset D004 SVDD VDD Rise Rate to ensure Power-on Reset D005 IDDP D010 IDD Min. Typ.(1) Max. Units 2.0 — 5.5 V See Figure 15-1 Conditions — 1.
PIC16F527 15.2 DC Characteristics: PIC16F527 (Extended) Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +125C (extended) DC Characteristics Param No. D001 Sym. VDD Characteristic Supply Voltage Voltage(2) D002 VDR RAM Data Retention D003 VPOR VDD Start Voltage to ensure Power-on Reset D004 SVDD VDD Rise Rate to ensure Power-on Reset D005 IDDP D010 IDD Min. Typ.(1) Max. Units 2.0 — 5.5 V See Figure 15-1 Conditions — 1.
PIC16F527 TABLE 15-1: DC CHARACTERISTICS: PIC16F527 (Industrial, Extended) Standard Operating Conditions (unless otherwise specified) Operating temperature -40°C TA +85°C (industrial) -40°C TA +125°C (extended) Operating voltage VDD range as described in DC spec. DC CHARACTERISTICS Param No. Sym. VIL Characteristic Min. Typ.† Max. Units Conditions Input Low Voltage I/O ports D030 with TTL buffer D030A Vss — 0.8 V For all 4.5 VDD 5.5V Vss — 0.
PIC16F527 TABLE 15-2: COMPARATOR SPECIFICATIONS Comparator Specifications Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C to 125°C Characteristics Sym. Min. Typ. Max. Units 0.70 V Internal Voltage Reference VIVRF 0.50 0.60 Input offset voltage VOS — 5.0 — mV Input common mode voltage* VCM 0 — VDD – 1.
PIC16F527 TABLE 15-4: OPERATIONAL AMPLIFIER (OPA) MODULE DC SPECIFICATIONS Standard Operating Conditions (unless otherwise stated) VCM = 0V, VOUT = VDD/2, VDD = 5.0V, VSS = 0V, CL = 50 pF, RL = 100k Operating temperature -40°C TA +125°C OPA DC CHARACTERISTICS Param No. Sym. Characteristics Min. Typ. Max.
PIC16F527 TABLE 15-6: A/D CONVERTER CHARACTERISTICS A/D Converter Specifications Param No. A01 Sym. Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +125°C Characteristic Min. Typ.† Max. Units 8 bit Conditions NR Resolution — — Integral Error — — 1.5 — — -1< EDNL 1.7 — — 1.5 LSb VDD = 5.0V -0.7 — +2.2 LSb VDD = 5.
PIC16F527 15.3 Timing Parameter Symbology and Load Conditions The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 2.
PIC16F527 TABLE 15-8: EXTERNAL CLOCK TIMING REQUIREMENTS AC CHARACTERISTICS Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +85C (industrial), -40C TA +125C (extended) Operating Voltage VDD range is described in Section 15.1 “DC Characteristics: PIC16F527 (Industrial)” Param No. Sym. Characteristic Min. Typ.
PIC16F527 TABLE 15-9: CALIBRATED INTERNAL RC FREQUENCIES AC CHARACTERISTICS Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +85C (industrial), -40C TA +125C (extended) Operating Voltage VDD range is described in Section 15.1 “DC Characteristics: PIC16F527 (Industrial)” Param No. Freq. Min. Tolerance F10 Sym. FOSC Characteristic Internal Calibrated INTOSC Frequency(1) Typ.† Max. Units Conditions 1% 7.92 8.00 8.08 MHz 3.
PIC16F527 TABLE 15-10: TIMING REQUIREMENTS Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +85C (industrial) AC -40C TA +125C (extended) CHARACTERISTICS Operating Voltage VDD range is described in Section 15.1 “DC Characteristics: PIC16F527 (Industrial)” Param No. Sym. Characteristic Min. Typ.(1) Max.
PIC16F527 TABLE 15-11: RESET, WATCHDOG TIMER AND DEVICE RESET TIMER Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +85C (industrial) -40C TA +125C (extended) Operating Voltage VDD range is described in Section 15.1 “DC Characteristics: PIC16F527 (Industrial)” AC CHARACTERISTICS Param No. Typ.(1) Max. Units Conditions Sym. Characteristic Min. 30 TMCL MCLR Pulse Width (low) 2000* — — ns VDD = 5.
PIC16F527 TABLE 15-13: FLASH DATA MEMORY WRITE/ERASE TIME Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +85C (industrial) -40C TA +125C (extended) Operating Voltage VDD range is described in Section 15.1 “DC Characteristics: PIC16F527 (Industrial)” AC CHARACTERISTICS Param No. Sym. 43 TDW 44 TDE * Note 1: Min. Typ.(1) Max. Units Flash Data Memory Write Cycle Time 2 3.5 5 ms Flash Data Memory Erase Cycle Time 2 3.
PIC16F527 16.0 DC AND AC CHARACTERISTICS GRAPHS AND CHARTS Graphs and tables are not available at this time. 2012 Microchip Technology Inc.
PIC16F527 NOTES: DS41652A-page 100 Preliminary 2012 Microchip Technology Inc.
PIC16F527 17.0 PACKAGING INFORMATION 17.1 Package Marking Information 20-Lead PDIP (300 mil) Example XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN PIC16F527 -E/P e3 1220123 20-Lead SOIC (7.50 mm) Example PIC16F527 -E/SO e3 1220123 Legend: XX...
PIC16F527 Package Marking Information (Continued) 20-Lead SSOP (5.30 mm) Example PIC16F527 -E/SS e3 1220123 20-Lead QFN (4x4x0.9 mm) Example PIN 1 PIN 1 Legend: XX...X Y YY WW NNN e3 * Note: * PIC16 F527 E/ML e3 220123 Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free.
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PIC16F527 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS41652A-page 104 Preliminary 2012 Microchip Technology Inc.
PIC16F527 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2012 Microchip Technology Inc.
PIC16F527 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS41652A-page 106 Preliminary 2012 Microchip Technology Inc.
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PIC16F527 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS41652A-page 108 Preliminary 2012 Microchip Technology Inc.
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PIC16F527 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ DS41652A-page 110 Preliminary 2012 Microchip Technology Inc.
PIC16F527 APPENDIX A: DATA SHEET REVISION HISTORY Revision A (09/2012) Initial release of this document. 2012 Microchip Technology Inc.
PIC16F527 NOTES: DS41652A-page 112 Preliminary 2012 Microchip Technology Inc.
PIC16F527 INDEX A M A/D Memory Organization ......................................................... 15 Memory Map............................................................... 15 PIC16F527 ................................................................. 15 Program Memory (PIC16F527) .................................. 15 Microchip Internet Web Site.............................................. 115 MPLAB ASM30 Assembler, Linker, Librarian .....................
PIC16F527 STATUS Register................................................................ 19 STATUS register ................................................................. 51 Status Register................................................................ 9, 19 T Timer0 Timer0 ......................................................................... 35 Timer0 (TMR0) Module ............................................... 35 TMR0 with External Clock...........................................
PIC16F527 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers.
PIC16F527 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document.
PIC16F527 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX XXX Device Temperature Range Package Pattern Examples: a) b) c) Device: PIC16F527 Temperature Range: I E Package: P SO SS ML Pattern: Special Requirements d) = = -40C to +85C (Industrial) -40C to +125C (Extended) = = = = PIC16F527-E/P 301 = Extended Temp., PDIP package, QTP pattern #301 PIC16F527-I/SO = Industrial Temp.
PIC16F527 NOTES: DS41652A-page 118 Preliminary 2012 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
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