Datasheet

PIC16F526
DS41326E-page 50  2010 Microchip Technology Inc.
8.3.1 MCLR ENABLE
This Configuration bit, when unprogrammed (left in the
‘1’ state), enables the external MCLR
function. When
programmed, the MCLR
function is tied to the internal
V
DD and the pin is assigned to be a I/O. See Figure 8-6.
FIGURE 8-6: MCLR SELECT
8.4 Power-on Reset (POR)
The PIC16F526 device incorporates an on-chip Power-
on Reset (POR) circuitry, which provides an internal
chip Reset for most power-up situations.
The on-chip POR circuit holds the chip in Reset until
V
DD has reached a high enough level for proper oper-
ation. To take advantage of the internal POR, program
the RB3/MCLR/VPP pin as MCLR and tie through a
resistor to V
DD, or program the pin as RB3. An internal
weak pull-up resistor is implemented using a transistor
(refer to Table 14-5 for the pull-up resistor ranges). This
will eliminate external RC components usually needed
to create a Power-on Reset. A maximum rise time for
V
DD is specified. See Section 14.0 “Electrical Char-
acteristics” for details.
When the device starts normal operation (exit the
Reset condition), device operating parameters (volt-
age, frequency, temperature,...) must be met to ensure
operation. If these conditions are not met, the device
must be held in Reset until the operating parameters
are met.
A simplified block diagram of the on-chip Power-on
Reset circuit is shown in Figure 8-7.
The Power-on Reset circuit and the Device Reset
Timer (see Section 8.5 “Device Reset Timer (DRT)”)
circuit are closely related. On power-up, the Reset latch
is set and the DRT is reset. The DRT timer begins
counting once it detects MCLR
to be high. After the
time-out period, which is typically 18 ms or 1 ms, it will
reset the Reset latch and thus end the on-chip Reset
signal.
A power-up example where MCLR
is held low is shown
in Figure 8-8. V
DD is allowed to rise and stabilize before
bringing MCLR
high. The chip will actually come out of
Reset T
DRT msec after MCLR goes high.
In Figure 8-9, the on-chip Power-on Reset feature is
being used (MCLR and VDD are tied together or the pin
is programmed to be RB3. The V
DD is stable before the
start-up timer times out and there is no problem in get-
ting a proper Reset. However, Figure 8-10 depicts a
problem situation where V
DD rises too slowly. The time
between when the DRT senses that MCLR
is high and
when MCLR
and VDD actually reach their full value, is
too long. In this situation, when the start-up timer times
out, V
DD has not reached the VDD (min) value and the
chip may not function correctly. For such situations, we
recommend that external RC circuits be used to
achieve longer POR delay times (Figure 8-9).
For additional information, refer to Application Notes
AN522 “Power-Up Considerations” (DS00522) and
AN607 “Power-up Trouble Shooting” (DS00607).
RB3/MCLR/VPP
MCLRE
Internal MCLR
RBWU
Note: When the device starts normal operation
(exit the Reset condition), device operat-
ing parameters (voltage, frequency, tem-
perature, etc.) must be met to ensure
operation. If these conditions are not met,
the device must be held in Reset until the
operating conditions are met.