Datasheet

PIC16F526

DS41326E-page 44  2010 Microchip Technology Inc.

CPDF IOSCFS MCLRE CP WDTE FOSC2 FOSC1 FOSC0

bit 7 bit 0

bit 7 CP

DF: Code Protection bit – Flash Data Memory

1 = Code protection off

0 = Code protection on

bit 6 IOSCFS: Internal Oscillator Frequency Select bit

1 = 8 MHz INTOSC frequency

0 = 4 MHz INTOSC frequency

bit 5 MCLRE: Master Clear Enable bit

1 = RB3/MCLR

pin functions as MCLR

0 = RB3/MCLR pin functions as RB3, MCLR internally tied to VDD

bit 4 CP: Code Protection bit – User Program Memory

1 = Code protection off

0 = Code protection on

bit 3 WDTE: Watchdog Timer Enable bit

1 = WDT enabled

0 = WDT disabled

bit 2-0 FOSC<2:0>: Oscillator Selection bits

000 = LP oscillator and 18 ms DRT

001 = XT oscillator and 18 ms DRT

010 = HS oscillator and 18 ms DRT

011 = EC oscillator with RB4 function on RB4/OSC2/CLKOUT and 1 ms DRT

(1)

100 = INTRC with RB4 function on RB4/OSC2/CLKOUT and 1 ms DRT

(1)

101 = INTRC with CLKOUT function on RB4/OSC2/CLKOUT and 1 ms DRT

(1)

110 = EXTRC with RB4 function on RB4/OSC2/CLKOUT and 1 ms DRT

(1)

111 = EXTRC with CLKOUT function on RB4/OSC2/CLKOUT and 1 ms DRT

(1)

Note 1: Refer to the “PIC16F526 Memory Programming Specification”, DS41317 to determine how to access the

Configuration Word.

2: DRT length (18 ms or 1 ms) is a function of Clock mode selection. It is the responsibility of the application

designer to ensure the use of either 18 ms (nominal) DRT or the 1 ms (nominal) DRT will result in

acceptable operation. Refer to Section 14.1 “DC Characteristics: PIC16F526 (Industrial)” and

Section 14.2 “DC Characteristics: PIC16F526 (Extended)” for V

DD rise time and stability requirements

for this mode of operation.