Datasheet

 2010 Microchip Technology Inc. DS41326E-page 25

PIC16F526

5.4 Code Protection

Code protection does not prevent the CPU from

performing read or write operations on the Flash data

memory. Refer to the code protection chapter for more

information.

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0

R/W-0

— — — FREE WRERR WREN WR

bit 7

bit 0

Legend:

S = Bit can only be set

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-5 Unimplemented: Read as ‘0’.

bit 4 FREE: Flash Data Memory Row Erase Enable Bit

1 = Program memory row being pointed to by EEADR will be erased on the next write cycle. No write

will be performed. This bit is cleared at the completion of the erase operation.

0 = Perform write only

bit 3 WRERR: Write Error Flag bit

1 = A write operation terminated prematurely (by device Reset)

0 = Write operation completed successfully

bit 2 WREN: Write Enable bit

1 = Allows write cycle to Flash data memory

0 = Inhibits write cycle to Flash data memory

bit 1 WR: Write Control bit

1 = Initiate a erase or write cycle

0 = Write/Erase cycle is complete

bit 0 RD: Read Control bit

1 = Initiate a read of Flash data memory

0 = Do not read Flash data memory