PIC16F526 Data Sheet 14-Pin, 8-Bit Flash Microcontroller 2010 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
PIC16F526 14-Pin, 8-Bit Flash Microcontroller High-Performance RISC CPU: Low-Power Features/CMOS Technology: • Only 33 Single-Word Instructions • All Single-Cycle Instructions except for Program Branches which are Two-Cycle • Two-Level Deep Hardware Stack • Direct, Indirect and Relative Addressing modes for Data and Instructions • Operating Speed: - DC – 20 MHz crystal oscillator - DC – 200 ns instruction cycle • On-chip Flash Program Memory: - 1024 x 12 • General Purpose Registers (SRAM): - 67 x 8 • Flas
PIC16F526 VDD 1 RB5/OSC1/CLKIN 2 3 RB4/OSC2/CLKOUT RC5/T0CKI 4 5 RC4/C2OUT 6 RC3 7 RB3/MCLR/VPP VSS 12 RB1/C1IN-/AN1/ICSPCLK 11 RB2/C1OUT/AN2 10 RC0/C2IN+ 9 RC1/C2IN- 8 RC2/CVREF RB0/C1IN+/AN0/ICSPDAT 3 RC5/T0CKI 4 NC GND RB1/C1IN-/AN1/ICSPCLK 10 RB2/C1OUT/AN2 9 5 6 7 8 RC1/C2IN- 2 RB3/MCLR/VPP RB0/C1IN+/AN0/ICSPDAT 11 RC2/CVREF RB4/OSC2/CLKOUT PIC16F526 16 15 14 13 12 RC3 1 RC4/C2OUT RB5/OSC1/CLKIN DS41326E-page 4 14 13 16-PIN QFN DIAGRAM VDD FIGURE 1-2
PIC16F526 Table of Contents 1.0 General Description..................................................................................................................................................................... 7 2.0 PIC16F526 Device Varieties ...................................................................................................................................................... 9 3.0 Architectural Overview ..................................................................................
PIC16F526 NOTES: DS41326E-page 6 2010 Microchip Technology Inc.
PIC16F526 1.0 GENERAL DESCRIPTION The PIC16F526 device from Microchip Technology is low-cost, high-performance, 8-bit, fully-static, Flashbased CMOS microcontrollers. It employs a RISC architecture with only 33 single-word/single-cycle instructions. All instructions are single cycle (200 s) except for program branches, which take two cycles. The PIC16F526 device delivers performance an order of magnitude higher than their competitors in the same price category.
PIC16F526 NOTES: DS41326E-page 8 2010 Microchip Technology Inc.
PIC16F526 2.0 PIC16F526 DEVICE VARIETIES A variety of packaging options are available. Depending on application and production requirements, the proper device option can be selected using the information in this section. When placing orders, please use the PIC16F526 Product Identification System at the back of this data sheet to specify the correct part number. 2.1 Quick Turn Programming (QTP) Devices 2.
PIC16F526 NOTES: DS41326E-page 10 2010 Microchip Technology Inc.
PIC16F526 3.0 ARCHITECTURAL OVERVIEW The high performance of the PIC16F526 device can be attributed to a number of architectural features commonly found in RISC microprocessors. To begin with, the PIC16F526 device uses a Harvard architecture in which program and data are accessed on separate buses. This improves bandwidth over traditional von Neumann architectures where program and data are fetched on the same bus.
PIC16F526 FIGURE 3-1: PIC16F526 BLOCK DIAGRAM 11 Flash Program Memory 1K x 12 Flash Data Memory 64x8 Program Bus 8 Data Bus Program Counter PORTB RB0/ICSPDAT RB1/ICSPCLK RB2 RB3/MCLR/VPP RB4/OSC2/CLKOUT RB5/OSC1/CLKIN RAM 67 bytes File Registers STACK1 STACK2 12 RAM Addr (1) 9 PORTC Addr MUX Instruction Reg Direct Addr 5 5-7 RC0 RC1 RC2 RC3 RC4 RC5/T0CKI Indirect Addr FSR Reg STATUS Reg 8 Device Reset Timer OSC1/CLKIN OSC2/CLKOUT Instruction Decode and Control Power-on Reset Timing
PIC16F526 TABLE 3-2: PIC16F526 PINOUT DESCRIPTION Name RB0//C1IN+/AN0/ ICSPDAT RB1/C1IN-/AN1/ ICSPCLK RB2/C1OUT/AN2 RB3/MCLR/VPP RB4/OSC2/CLKOUT RB5/OSC1/CLKIN RC0/C2IN+ RC1/C2INRC2/CVREF RC3 RC4/C2OUT RC5/T0CKI Function Input Type RB0 TTL C1IN+ AN Output Type Description CMOS Bidirectional I/O pin. Can be software programmed for internal weak pull-up and wake-up from Sleep on pin change. — Comparator 1 input. — ADC channel input. AN0 AN ICSPDAT ST CMOS ICSP™ mode Schmitt Trigger.
PIC16F526 3.1 Clocking Scheme/Instruction Cycle 3.2 Instruction Flow/Pipelining An instruction cycle consists of four Q cycles (Q1, Q2, Q3 and Q4). The instruction fetch and execute are pipelined such that fetch takes one instruction cycle, while decode and execute take another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the PC to change (e.g.
PIC16F526 4.1 Program Memory Organization for the PIC16F526 The PIC16F526 device has an 11-bit Program Counter (PC) capable of addressing a 2K x 12 program memory space. Program memory is partitioned into user memory, data memory and configuration memory spaces. The user memory space is the on-chip user program memory. As shown in Figure 4-1, it extends from 0x000 to 0x3FF and partitions into pages, including Reset vector at address 0x3FF.
PIC16F526 4.2 Data Memory (SRAM and FSRs) 4.2.1 Data memory is composed of registers or bytes of SRAM. Therefore, data memory for a device is specified by its register file. The register file is divided into two functional groups: Special Function Registers (SFR) and General Purpose Registers (GPR). The General Purpose Register file is accessed, either directly or indirectly, through the File Select Register (FSR). See Section 4.8 “Indirect Data Addressing: INDF and FSR Registers”.
PIC16F526 TABLE 4-1: Addr SPECIAL FUNCTION REGISTER (SFR) SUMMARY Name Bit 7 Bit 6 — — Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page # N/A TRIS --11 1111 27 N/A OPTION Contains control bits to configure Timer0 and Timer0/WDT prescaler 1111 1111 19 00h INDF Uses contents of FSR to Address Data Memory (not a physical register) xxxx xxxx 22 01h/41h TMR0 Timer0 Module Register xxxx xxxx 37 02h(1) PCL Low order 8 bits of PC 1111 1111 21 03h STATUS 0001 1xxx 18 04h FSR 05h/4
PIC16F526 4.3 STATUS Register For example, CLRF STATUS, will clear the upper three bits and set the Z bit. This leaves the STATUS register as 000u u1uu (where u = unchanged). This register contains the arithmetic status of the ALU, the Reset status and the page preselect bit. Therefore, it is recommended that only BCF, BSF and MOVWF instructions be used to alter the STATUS register. These instructions do not affect the Z, DC or C bits from the STATUS register.
PIC16F526 4.4 OPTION Register The OPTION register is a 8-bit wide, write-only register, which contains various control bits to configure the Timer0/WDT prescaler and Timer0. Note: By executing the OPTION instruction, the contents of the W register will be transferred to the OPTION register. A Reset sets the OPTION <7:0> bits. REGISTER 4-2: If TRIS bit is set to ‘0’, the wake-up on change and pull-up functions are disabled for that pin (i.e., note that TRIS overrides Option control of RBPU and RBWU).
PIC16F526 4.5 OSCCAL Register The Oscillator Calibration (OSCCAL) register is used to calibrate the 8 MHz internal oscillator macro. It contains 7 bits of calibration that uses a two’s complement scheme for controlling the oscillator speed. See Register 4-3 for details.
PIC16F526 4.6 Program Counter 4.6.1 EFFECTS OF RESET As a program instruction is executed, the Program Counter (PC) will contain the address of the next program instruction to be executed. The PC value is increased by one every instruction cycle, unless an instruction changes the PC. The PC is set upon a Reset, which means that the PC addresses the last location in the last page (i.e., the oscillator calibration instruction).
PIC16F526 4.8 Indirect Data Addressing: INDF and FSR Registers A simple program to clear RAM locations 10h-1Fh using indirect addressing is shown in Example 4-1. The INDF Register is not a physical register. Addressing INDF actually addresses the register whose address is contained in the FSR Register (FSR is a pointer). This is indirect addressing. EXAMPLE 4-1: Reading INDF itself indirectly (FSR = 0) will produce 00h.
PIC16F526 5.0 FLASH DATA MEMORY CONTROL The Flash data memory is readable and writable during normal operation (full VDD range). This memory is not directly mapped in the register file space. Instead, it is indirectly addressed through the Special Function Registers (SFRs). 5.
PIC16F526 5.2.2 WRITING TO FLASH DATA MEMORY Note 1: Only a series of BSF commands will work to enable the memory write sequence documented in Example 2. No other sequence of commands will work, no exceptions. Once a cell is erased, new data can be written. Program execution is suspended during the write cycle. The following sequence must be performed for a single byte write. 1. 2. 3. 4.
PIC16F526 REGISTER 5-3: EECON: FLASH CONTROL REGISTER U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — FREE WRERR WREN WR RD bit 7 bit 0 Legend: S = Bit can only be set R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’.
PIC16F526 NOTES: DS41326E-page 26 2010 Microchip Technology Inc.
PIC16F526 6.0 I/O PORT 6.2 PORTC is a 6-bit I/O register. Only the low-order 6 bits are used (RC<5:0>). Bits 7 and 6 are unimplemented and read as ‘0’s. As with any other register, the I/O register(s) can be written and read under program control. However, read instructions (e.g., MOVF PORTB,W) always read the I/O pins independent of the pin’s Input/Output modes. On Reset, all I/O ports are defined as input (inputs are at highimpedance) since the I/O control registers are all set. 6.1 6.
PIC16F526 REGISTER 6-2: PORTC: PORTC REGISTER U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — — RC5 RC4 RC3 RC2 RC1 RC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RC<5:0>: PORTC I/O Pin bits 1 = Port pin is >VIH min. 0 = Port pin is
PIC16F526 6.4 I/O Interfacing The equivalent circuit for an I/O port pin is shown in Figure 6-1. All port pins, except RB3 which is inputonly, may be used for both input and output operations. For input operations, these ports are non-latching. Any input must be present until read by an input instruction (e.g., MOVF PORTB, W). The outputs are latched and remain unchanged until the output latch is rewritten. To use a port pin as output, the corresponding direction control bit in TRIS must be cleared (= 0).
PIC16F526 FIGURE 6-2: BLOCK DIAGRAM OF RB2 C1OUT Data Bus WR Port D Q 0 FIGURE 6-3: BLOCK DIAGRAM OF RB3 (with Weak Pull-up and Wake-up on Change) I/O Pin(1) 1 Data Latch GPPU RBPU MCLRE Q CK C1OUTEN W Reg TRIS ‘f’ D Reset Q TRIS Latch Input Pin Q CK Reset ADC Pin Enable Data Bus RD Port Q D CK RD Port Pin Change ADC Note 1: I/O pins have protection diodes to VDD and VSS. DS41326E-page 30 Note 1: RB3/MCLR pin has a protection diode to VSS only. 2010 Microchip Technology Inc.
PIC16F526 FIGURE 6-4: BLOCK DIAGRAM OF RB4 (with Weak Pull-up and Wake-up on Change) D Q 0 Q CK I/O pin(1) 1 D Q Data Latch I/O pin(1) Q CK D Q TRIS Latch TRIS ‘f’ Q CK FOSC/4 W Reg BLOCK DIAGRAM OF RB5 D W Reg Data Latch WR Port Data Bus WR Port RBPU Data Bus FIGURE 6-5: Reset (Note 2) Q TRIS Latch TRIS ‘f’ Q CK RD Port Reset OSC2 INTOSC/RC/EC (Note 3) CLKOUT Enable (Note 2) Note 1: Oscillator Circuit I/O pins have protection diodes to VDD and VSS.
PIC16F526 FIGURE 6-6: Data Bus WR Port W Reg TRIS ‘f’ BLOCK DIAGRAM OF RC0/RC1 D FIGURE 6-7: BLOCK DIAGRAM OF RC2 VROE Q CVREF Data Latch I/O pin(1) Q CK Data Bus WR Port D Q D Q 1 I/O PIN(1) 0 Data Latch Q CK TRIS Latch W Reg Q CK Reset TRIS ‘f’ D Q TRIS Latch Q CK Comp Pin Enable Reset RD Port COMP2 Note 1: I/O pins have protection diodes to VDD and VSS. DS41326E-page 32 RD Port Note 1: I/O pins have protection diodes to VDD and VSS. 2010 Microchip Technology Inc.
PIC16F526 FIGURE 6-8: Data Bus WR Port W Reg TRIS ‘f’ BLOCK DIAGRAM OF RC3 FIGURE 6-9: BLOCK DIAGRAM OF RC4 C2OUT I/O Pin(1) D Q Data Latch Q CK Data Bus WR Port D Q 0 I/O Pin(1) 1 Data Latch Q CK C2OUTEN D Q TRIS Latch W Reg Q CK TRIS ‘f’ D Q TRIS Latch Q CK Reset Reset RD Port RD Port Note 1: I/O pins have protection diodes to VDD and VSS. 2010 Microchip Technology Inc. Note 1: I/O pins have protection diodes to VDD and VSS.
PIC16F526 FIGURE 6-10: Data Bus WR Port W Reg TRIS ‘f’ BLOCK DIAGRAM OF RC5 I/O Pin(1) D Q Data Latch Q CK D Q TRIS Latch Q CK T0CS Reset RD Port T0CKI Note 1: I/O pins have protection diodes to VDD and VSS. DS41326E-page 34 2010 Microchip Technology Inc.
PIC16F526 TABLE 6-2: Addr SUMMARY OF PORT REGISTERS Name Bit 7 Bit 6 — — RBWU RBPU N/A TRIS N/A OPTION 03h STATUS 06h PORTB — 07h PORTC — Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 I/O Control Register (PORTB, PORTC) Value on Power-On Reset Value on All Other Resets --11 1111 --11 1111 1111 1111 1111 1111 TOCS TOSE PSA PS2 PS1 PS0 PA0 TO PD Z DC C — RB5 RB4 RB3 RB2 RB1 RB0 --xx xxxx --uu uuuu — RC5 RC4 RC3 RC2 RC1 RC0 --xx xxxx --uu uuuu RBWUF CWUF 0
PIC16F526 6.5 I/O Programming Considerations 6.5.1 EXAMPLE 6-1: BIDIRECTIONAL I/O PORTS Some instructions operate internally as read followed by write operations. The BCF and BSF instructions, for example, read the entire port into the CPU, execute the bit operation and rewrite the result. Caution must be used when these instructions are applied to a port where one or more pins are used as input/outputs.
PIC16F526 7.0 TIMER0 MODULE AND TMR0 REGISTER The Timer0 module has the following features: • • • • 8-bit timer/counter register, TMR0 Readable and writable 8-bit software programmable prescaler Internal or external clock select: - Edge select for external clock Figure 7-1 is a simplified block diagram of the Timer0 module. Timer mode is selected by clearing the T0CS bit of the OPTION register. In Timer mode, the Timer0 module will increment every instruction cycle (without prescaler).
PIC16F526 FIGURE 7-2: PC (Program Counter) TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC – 1 Instruction Fetch PC PC + 1 MOVWF TMR0 T0 Timer0 T0 + 1 T0 + 2 Instruction Executed PC + 4 PC + 5 PC + 6 NT0 + 1 Read TMR0 reads NT0 Read TMR0 reads NT0 NT0 + 2 Read TMR0 Read TMR0 reads NT0 + 1 reads NT0 + 2 Read TMR0 reads NT0 TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2
PIC16F526 7.1 Using Timer0 with an External Clock When an external clock input is used for Timer0, it must meet certain requirements. The external clock requirement is due to internal phase clock (TOSC) synchronization. Also, there is a delay in the actual incrementing of Timer0 after synchronization. 7.1.1 EXTERNAL CLOCK SYNCHRONIZATION When no prescaler is used, the external clock input is the same as the prescaler output.
PIC16F526 7.2 Prescaler An 8-bit counter is available as a prescaler for the Timer0 module or as a postscaler for the Watchdog Timer (WDT), respectively (see Section 8.6 “Watchdog Timer (WDT)”). For simplicity, this counter is being referred to as “prescaler” throughout this data sheet. Note: The prescaler may be used by either the Timer0 module or the WDT, but not both. Thus, a prescaler assignment for the Timer0 module means that there is no prescaler for the WDT and vice versa.
PIC16F526 FIGURE 7-5: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER TCY (= FOSC/4) Data Bus 0 Comparator Output 0 1 8 M U X 1 0 1 T0CKI Pin M U X T0SE(1) T0CS(1) Sync 2 Cycles TMR0 Reg PSA(1) C1TOCS 0 Watchdog Timer 1 8-bit Prescaler M U X 8 PS<2:0>(1) 8-to-1 MUX (1) PSA WDT Enable bit 1 0 MUX PSA(1) WDT Time-out Note 1: T0CS, T0SE, PSA, PS<2:0> are bits in the OPTION register. 2010 Microchip Technology Inc.
PIC16F526 NOTES: DS41326E-page 42 2010 Microchip Technology Inc.
PIC16F526 8.0 SPECIAL FEATURES OF THE CPU What sets a microcontroller apart from other processors are special circuits that deal with the needs of real-time applications. The PIC16F526 microcontrollers have a host of such features intended to maximize system reliability, minimize cost through elimination of external components, provide powersaving operating modes and offer code protection.
PIC16F526 REGISTER 8-1: CPDF CONFIG: CONFIGURATION WORD REGISTER IOSCFS MCLRE CP WDTE FOSC2 FOSC1 bit 7 FOSC0 bit 0 bit 7 CPDF: Code Protection bit – Flash Data Memory 1 = Code protection off 0 = Code protection on bit 6 IOSCFS: Internal Oscillator Frequency Select bit 1 = 8 MHz INTOSC frequency 0 = 4 MHz INTOSC frequency bit 5 MCLRE: Master Clear Enable bit 1 = RB3/MCLR pin functions as MCLR 0 = RB3/MCLR pin functions as RB3, MCLR internally tied to VDD bit 4 CP: Code Protection bit – User
PIC16F526 8.2 Oscillator Configurations 8.2.1 FIGURE 8-1: OSCILLATOR TYPES The PIC16F526 device can be operated in up to six different oscillator modes. The user can program up to three Configuration bits (FOSC<2:0>). To select one of these modes: • • • • • • LP: XT: HS: INTRC: EXTRC: EC: 8.2.
PIC16F526 TABLE 8-2: CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR(2) Osc Type Resonator Freq. Cap. Range C1 Cap. Range C2 LP 32 kHz(1) 15 pF 15 pF XT 200 kHz 1 MHz 4 MHz 47-68 pF 15 pF 15 pF 47-68 pF 15 pF 15 pF 20 MHz 15-47 pF 15-47 pF HS Note 1: 2: 8.2.3 For VDD > 4.5V, C1 = C2 30 pF is recommended. These values are for design guidance only. Rs may be required to avoid overdriving crystals with low drive level specification.
PIC16F526 Also, see the Electrical Specifications section for variation of oscillator frequency due to VDD for given REXT/CEXT values, as well as frequency variation due to operating temperature for given R, C and VDD values. FIGURE 8-5: EXTERNAL RC OSCILLATOR MODE VDD REXT OSC1 Internal clock N CEXT PIC16F526 VSS FOSC/4 OSC2/CLKOUT 8.2.5 INTERNAL 4/8 MHz RC OSCILLATOR The internal RC oscillator provides a fixed 4/8 MHz (nominal) system clock at VDD = 5V and 25°C, (see Section 14.
PIC16F526 8.3 Reset The device differentiates between various kinds of Reset: • • • • • • Power-on Reset (POR) MCLR Reset during normal operation MCLR Reset during Sleep WDT Time-out Reset during normal operation WDT Time-out Reset during Sleep Wake-up from Sleep on pin change TABLE 8-3: Register W Some registers are not reset in any way, they are unknown on POR and unchanged in any other Reset.
PIC16F526 TABLE 8-4: RESET CONDITION FOR SPECIAL REGISTERS STATUS Addr: 03h Power-on Reset 0001 1xxx MCLR Reset during normal operation 000u uuuu MCLR Reset during Sleep 0001 0uuu WDT Reset during Sleep 0000 0uuu WDT Reset normal operation 0000 uuuu Wake-up from Sleep on pin change 1001 0uuu Wake-up from Sleep on comparator change 0101 0uuu Legend: u = unchanged, x = unknown, – = unimplemented bit, read as ‘0’. 2010 Microchip Technology Inc.
PIC16F526 8.3.1 MCLR ENABLE This Configuration bit, when unprogrammed (left in the ‘1’ state), enables the external MCLR function. When programmed, the MCLR function is tied to the internal VDD and the pin is assigned to be a I/O. See Figure 8-6. FIGURE 8-6: MCLR SELECT A power-up example where MCLR is held low is shown in Figure 8-8. VDD is allowed to rise and stabilize before bringing MCLR high. The chip will actually come out of Reset TDRT msec after MCLR goes high. RBWU RB3/MCLR/VPP MCLRE 8.
PIC16F526 FIGURE 8-7: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT VDD Power-up Detect POR (Power-on Reset) RB3/MCLR/VPP MCLR Reset S Q R Q MCLRE WDT Time-out Pin Change Sleep WDT Reset Start-up Timer (10 ms, 1.
PIC16F526 FIGURE 8-10: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): SLOW VDD RISE TIME V1 VDD MCLR Internal POR TDRT DRT Time-out Internal Reset Note: When VDD rises slowly, the TDRT time-out expires long before VDD has reached its final value. In this example, the chip will reset properly if, and only if, V1 VDD min. DS41326E-page 52 2010 Microchip Technology Inc.
PIC16F526 8.5 Device Reset Timer (DRT) On the PIC16F526 device, the DRT runs any time the device is powered up. DRT runs from Reset and varies based on oscillator selection and Reset type (see Table 8-5). The DRT operates on an internal RC oscillator. The processor is kept in Reset as long as the DRT is active. The DRT delay allows VDD to rise above VDD min. and for the oscillator to stabilize.
PIC16F526 FIGURE 8-11: WATCHDOG TIMER BLOCK DIAGRAM From Timer0 Clock Source (Figure 7-1) 0 1 Watchdog Time M U X Postscaler 8-to-1 MUX PS<2:0>(1) PSA WDT Enable Configuration Bit To Timer0 (Figure 7-4) 0 1 MUX PSA(1) WDT Time-out Note 1: TABLE 8-6: Address N/A PSA, PS<2:0> are bits in the OPTION register.
PIC16F526 8.7 Time-out Sequence, Power-down and Wake-up from Sleep Status Bits (TO, PD, RBWUF, CWUF) The TO, PD and RBWUF bits in the STATUS register can be tested to determine if a Reset condition has been caused by a power-up condition, a MCLR or Watchdog Timer (WDT) Reset.
PIC16F526 8.9 Power-down Mode (Sleep) A device may be powered down (Sleep) and later powered up (wake-up from Sleep). 8.9.1 SLEEP 8.9.2 The device can wake-up from Sleep through one of the following events: 1. The Power-Down mode is entered by executing a SLEEP instruction. 2. If enabled, the Watchdog Timer will be cleared but keeps running, the TO bit of the STATUS register is set, the PD bit of the STATUS register is cleared and the oscillator driver is turned off.
PIC16F526 8.10 Program Verification/Code Protection FIGURE 8-15: If the code protection bit has not been programmed, the on-chip program memory can be read out for verification purposes. The first 64 locations and the last location (OSCCAL) can be read, regardless of the code protection bit setting. The last memory location can be read regardless of the code protection bit setting on the PIC16F526 device. 8.
PIC16F526 NOTES: DS41326E-page 58 2010 Microchip Technology Inc.
PIC16F526 9.0 ANALOG-TO-DIGITAL (A/D) CONVERTER Note: The A/D Converter allows conversion of an analog signal into an 8-bit digital signal. 9.1 Clock Divisors The ADC has 4 clock source settings ADCS<1:0>. There are 3 divisor values 16, 8 and 4. The fourth setting is INTOSC with a divisor of 4. These settings will allow a proper conversion when using an external oscillator at speeds from 20 MHz to 350 kHz.
PIC16F526 9.1.5 SLEEP This ADC does not have a dedicated ADC clock, and therefore, no conversion in Sleep is possible. If a conversion is underway and a Sleep command is executed, the GO/DONE and ADON bit will be cleared. This will stop any conversion in process and powerdown the ADC module to conserve power. Due to the nature of the conversion process, the ADRES may contain a partial conversion. At least 1 bit must have been converted prior to Sleep to have partial conversion data in ADRES.
PIC16F526 9.1.6 ANALOG CONVERSION RESULT REGISTER right shifts of the ‘leading one’ have taken place, the conversion is complete; the ‘leading one’ has been shifted out and the GO/DONE bit is cleared. The ADRES register contains the results of the last conversion. These results are present during the sampling period of the next analog conversion process. After the sampling period is over, ADRES is cleared (= 0).
PIC16F526 REGISTER 9-2: ADRES: A/D CONVERSION RESULTS REGISTER R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X ADRES7 ADRES6 ADRES5 ADRES4 ADRES3 ADRES2 ADRES1 ADRES0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared EXAMPLE 9-1: PERFORMING AN ANALOG-TO-DIGITAL CONVERSION EXAMPLE 9-2: ;Sample code operates out of BANK0 loop0 MOVLW 0xF1 ;configure A/D MOVWF ADCON0 BSF ADCON0, 1 ;start
PIC16F526 10.0 COMPARATOR(S) This device contains two comparators comparator voltage reference.
PIC16F526 REGISTER 10-2: CM2CON0: COMPARATOR C2 CONTROL REGISTER R-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 C2OUT C2OUTEN C2POL C2PREF2 C2ON C2NREF C2PREF1 C2WU bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 C2OUT: Comparator Output bit 1 = VIN+ > VIN0 = VIN+ < VIN- bit 6 C2OUTEN: Comparator Output Enable bit(1), (2) 1 = Output of comparator is NOT placed on the C2OUT pin 0
PIC16F526 FIGURE 10-1: COMPARATORS BLOCK DIAGRAM RB2/C1OUT C1PREF C1IN+ 1 C1IN- 0 C1OUT (Register) 1 VREF (0.6V) C1OUTEN + - 0 C1NREF C1ON C1POL 0 T0CKI 1 T0CKI Pin C1T0CS Q D S RC4/C2OUT C2PREF1 C2IN+ 1 0 1 READ CM1CON0 C2OUTEN + C2OUT (Register) 0 - C2PREF2 C2INC2ON C2POL 1 0 CVREF C2NREF Q D C1WU S CWUF READ CM2CON0 C2WU 2010 Microchip Technology Inc.
PIC16F526 10.1 Comparator Operation A single comparator is shown in Figure 10-2 along with the relationship between the analog input levels and the digital output. When the analog input at VIN+ is less than the analog input VIN-, the output of the comparator is a digital low level. The shaded area of the output of the comparator in Figure 10-2 represent the uncertainty due to input offsets and response time. See Table 14-2 for Common Mode Voltage.
PIC16F526 FIGURE 10-3: ANALOG INPUT MODE VDD VT = 0.6V RS < 10 K AIN CPIN 5 pF VA VT = 0.
PIC16F526 NOTES: DS41326E-page 68 2010 Microchip Technology Inc.
PIC16F526 11.0 COMPARATOR VOLTAGE REFERENCE MODULE 11.2 The Comparator Voltage Reference module also allows the selection of an internally generated voltage reference for one of the C2 comparator inputs. The VRCON register (Register 11-1) controls the Voltage Reference module shown in Figure 11-1. 11.1 Configuring The Voltage Reference The voltage reference can output 32 voltage levels; 16 in a high range and 16 in a low range.
PIC16F526 FIGURE 11-1: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM 16 Stages 8R R R R R VDD 8R VRR 16-1 Analog MUX VREN CVREF to Comparator 2 Input VR<3:0> RC2/CVREF VREN VR<3:0> = 0000 VRR VROE TABLE 11-1: Name VRCON REGISTERS ASSOCIATED WITH COMPARATOR VOLTAGE REFERENCE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR Value on all other Resets uuu- uuuu VREN VROE VRR — VR3 VR2 VR1 VR0 001- 1111 CM1CON0 C1OUT C1OUTEN C1POL C1T0CS C1ON C1NREF C1PREF C1WU
PIC16F526 12.0 INSTRUCTION SET SUMMARY The PIC16 instruction set is highly orthogonal and is comprised of three basic categories. • Byte-oriented operations • Bit-oriented operations • Literal and control operations Each PIC16 instruction is a 12-bit word divided into an opcode, which specifies the instruction type, and one or more operands which further specify the operation of the instruction.
PIC16F526 TABLE 12-2: Mnemonic, Operands ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF INSTRUCTION SET SUMMARY Description Cycles 12-Bit Opcode MSb LSb Status Notes Affected f, d f, d f — f, d f, d f, d f, d f, d f, d f, d f — f, d f, d f, d f, d f, d 0001 11df ffff C, DC, Z 1, 2, 4 Add W and f 1 0001 01df ffff AND W with f 1 Z 2, 4 0000 011f ffff Clear f 1 Z 4 0000 0100 0000 Clear W 1 Z 0010 01df ffff Complement f 1 Z 0000 11df ffff Decrement f 1 Z
PIC16F526 ADDWF Add W and f BCF f,d Bit Clear f Syntax: [ label ] ADDWF Syntax: [ label ] BCF Operands: 0 f 31 d 01 Operands: 0 f 31 0b7 Operation: (W) + (f) (dest) Operation: 0 (f) Status Affected: C, DC, Z Status Affected: None Description: Description: Bit ‘b’ in register ‘f’ is cleared.
PIC16F526 BTFSS Bit Test f, Skip if Set CLRW Syntax: [ label ] BTFSS f,b Syntax: [ label ] CLRW 0 f 31 0b<7 Operands: None Operation: 00h (W); 1Z Operands: Clear W Operation: skip if (f) = 1 Status Affected: None Status Affected: Z Description: If bit ‘b’ in register ‘f’ is ‘1’, then the next instruction is skipped.
PIC16F526 DECF Decrement f INCF Syntax: [ label ] DECF f,d Syntax: [ label ] Operands: 0 f 31 d [0,1] Operands: 0 f 31 d [0,1] Operation: (f) – 1 (dest) Operation: (f) + 1 (dest) Status Affected: Z Status Affected: Z Description: Decrement register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. Description: The contents of register ‘f’ are incremented.
PIC16F526 IORWF Inclusive OR W with f MOVWF Syntax: [ label ] Syntax: [ label ] Operands: 0 f 31 d [0,1] Operands: 0 f 31 (W).OR. (f) (dest) Operation: (W) (f) Operation: Status Affected: None Status Affected: Z Description: Description: Inclusive OR the W register with register ‘f’. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is placed back in register ‘f’. Move data from the W register to register ‘f’.
PIC16F526 RETLW Return with Literal in W SLEEP Enter SLEEP Mode Syntax: [ label ] Syntax: [label ] Operands: 0 k 255 Operands: None Operation: k (W); TOS PC Operation: 00h WDT; 0 WDT prescaler; 1 TO; 0 PD RETLW k SLEEP Status Affected: None Description: The W register is loaded with the eight-bit literal ‘k’. The program counter is loaded from the top of the stack (the return address). This is a two-cycle instruction.
PIC16F526 TRIS Load TRIS Register XORWF Syntax: [ label ] TRIS Syntax: [ label ] XORWF Operands: f=6 Operands: Operation: (W) TRIS register f 0 f 31 d [0,1] f Exclusive OR W with f f,d Status Affected: None Operation: (W) .XOR. (f) dest) Description: TRIS register ‘f’ (f = 6 or 7) is loaded with the contents of the W register Status Affected: Z Description: Exclusive OR the contents of the W register with register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register.
PIC16F526 13.
PIC16F526 13.2 MPLAB C Compilers for Various Device Families The MPLAB C Compiler code development systems are complete ANSI C compilers for Microchip’s PIC18, PIC24 and PIC32 families of microcontrollers and the dsPIC30 and dsPIC33 families of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. 13.
PIC16F526 13.7 MPLAB SIM Software Simulator The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC® DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis.
PIC16F526 13.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express 13.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits The PICkit™ 2 Development Programmer/Debugger is a low-cost development tool with an easy to use interface for programming and debugging Microchip’s Flash families of microcontrollers.
PIC16F526 14.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings(†) Ambient temperature under bias.......................................................................................................... -40°C to +125°C Storage temperature ............................................................................................................................ -65°C to +150°C Voltage on VDD with respect to VSS ...........................................................................................
PIC16F526 PIC16F526 VOLTAGE-FREQUENCY GRAPH, -40C TA +125C FIGURE 14-1: 6.0 5.5 5.0 VDD (Volts) 4.5 4.0 3.5 3.0 INTOSC OR EC MODE ONLY 2.5 2.0 0 4 20 10 25 Frequency (MHz) FIGURE 14-2: MAXIMUM OSCILLATOR FREQUENCY TABLE Oscillator Mode LP XT XTRC INTOSC EC HS 0 200 kHz 4 MHz 8 MHz 20 MHz Frequency DS41326E-page 84 2010 Microchip Technology Inc.
PIC16F526 14.1 DC Characteristics: PIC16F526 (Industrial) Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +85C (industrial) DC Characteristics Param No. Sym. Characteristic Min. Typ.(1) Max. Units Conditions D001 VDD Supply Voltage 2.0 5.5 V See Figure 14-1 D002 VDR RAM Data Retention Voltage(2) — 1.5* — V Device in Sleep mode D003 VPOR VDD Start Voltage to ensure Power-on Reset — Vss — V See Section 8.
PIC16F526 14.2 DC Characteristics: PIC16F526 (Extended) Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +125C (extended) DC Characteristics Param No. Sym. Characteristic Min. Typ.(1) Max. Units Conditions D001 VDD Supply Voltage 2.0 5.5 V See Figure 14-1 D002 VDR RAM Data Retention Voltage(2) — 1.5* — V Device in Sleep mode D003 VPOR VDD Start Voltage to ensure Power-on Reset — Vss — V See Section 8.
PIC16F526 TABLE 14-1: DC CHARACTERISTICS: PIC16F526 (Industrial, Extended) Standard Operating Conditions (unless otherwise specified) Operating temperature -40°C TA +85°C (industrial) -40°C TA +125°C (extended) Operating voltage VDD range as described in DC spec. DC CHARACTERISTICS Param Sym. No. VIL Characteristic Min. Typ.† Max. Units Conditions Input Low Voltage I/O ports D030 with TTL buffer D030A Vss — 0.8 V For all 4.5 VDD 5.5V Vss — 0.
PIC16F526 TABLE 14-2: COMPARATOR SPECIFICATIONS. Comparator Specifications Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C to 125°C Characteristics Sym. Min. Typ. Max. Units 0.70 V Internal Voltage Reference VIVRF 0.50 0.60 Input offset voltage VOS — 5.0 10 mV Input common mode voltage* VCM 0 — VDD – 1.
PIC16F526 TABLE 14-4: A/D CONVERTER CHARACTERISTICS: A/D Converter Specifications Param No. A01 Sym. Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +125°C Characteristic Min. Typ.† Max. Units 8 bit Conditions NR Resolution — — Integral Error — — 1.5 — — -1< EDNL 1.7 — — 1.5 LSb VDD = 5.0V -0.7 — +2.2 LSb VDD = 5.
PIC16F526 14.3 Timing Parameter Symbology and Load Conditions The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 2.
PIC16F526 FIGURE 14-4: EXTERNAL CLOCK TIMING Q4 Q1 Q3 Q2 Q4 Q1 OSC1 1 3 3 4 4 2 TABLE 14-6: EXTERNAL CLOCK TIMING REQUIREMENTS AC CHARACTERISTICS Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +85C (industrial), -40C TA +125C (extended) Operating Voltage VDD range is described in Section 14.1 “DC Characteristics: PIC16F526 (Industrial)” Param No. Sym. Characteristic Min. Typ.(1) Max.
PIC16F526 TABLE 14-7: CALIBRATED INTERNAL RC FREQUENCIES AC CHARACTERISTICS Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +85C (industrial), -40C TA +125C (extended) Operating Voltage VDD range is described in Section 14.1 “DC Characteristics: PIC16F526 (Industrial)” Param No. Freq. Min. Tolerance F10 Sym. FOSC Characteristic Internal Calibrated INTOSC Frequency(1) Typ.† Max. Units Conditions 1% 7.92 8.00 8.08 MHz 3.
PIC16F526 FIGURE 14-5: I/O TIMING Q1 Q4 Q2 Q3 OSC1 I/O Pin (input) 17 I/O Pin (output) 19 18 New Value Old Value 20, 21 Note: All tests must be done with specified capacitive loads (see data sheet) 50 pF on I/O pins and CLKOUT. TABLE 14-8: TIMING REQUIREMENTS Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +85C (industrial) AC -40C TA +125C (extended) CHARACTERISTICS Operating Voltage VDD range is described in Section 14.
PIC16F526 FIGURE 14-6: RESET, WATCHDOG TIMER AND DEVICE RESET TIMER TIMING VDD MCLR 30 Internal POR 32 32 32 DRT Time-out(2) Internal Reset Watchdog Timer Reset 31 34 34 I/O pin(1) Note 1: 2: I/O pins must be taken out of High-Impedance mode by enabling the output drivers in software. Runs in MCLR or WDT Reset only in XT, LP and HS modes.
PIC16F526 FIGURE 14-7: TIMER0 CLOCK TIMINGS T0CKI 40 41 42 TABLE 14-10: TIMER0 CLOCK REQUIREMENT Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +85C (industrial) -40C TA +125C (extended) Operating Voltage VDD range is described in Section 14.1 “DC Characteristics: PIC16F526 (Industrial)” AC CHARACTERISTICS Param Sym. No.
PIC16F526 TABLE 14-11: FLASH DATA MEMORY WRITE/ERASE TIME Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +85C (industrial) -40C TA +125C (extended) Operating Voltage VDD range is described in Section 14.1 “DC Characteristics: PIC16F526 (Industrial)” AC CHARACTERISTICS Param No. Sym. 43 TDW 44 TDE * Note 1: Min. Typ.(1) Max. Units Flash Data Memory Write Cycle Time 2 3.5 5 ms Flash Data Memory Erase Cycle Time 2 3.
PIC16F526 15.0 DC AND AC CHARACTERISTICS GRAPHS AND CHARTS The graphs and tables provided in this section are for design guidance and are not tested. In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD range).
PIC16F526 FIGURE 15-2: TYPICAL IDD vs. FOSC OVER VDD (XT, EXTRC mode) 800 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 700 600 IDD (A) 500 5V 400 300 200 2V 100 0 0 1 3 2 5 4 FOSC (MHz) FIGURE 15-3: MAXIMUM IDD vs.
PIC16F526 FIGURE 15-4: IDD vs. VDD OVER FOSC (LP MODE) 120 Typical: Statistical Mean @25°C Industrial: Mean (Worst-Case Temp) + 3σ (-40°C to 85°C) Extended: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) 100 32 kHz Maximum Extended IDD (A) 80 60 32 kHz Maximum Industrial 32 kHz Typical 40 20 0 1 2 3 4 5 6 VDD (V) 2010 Microchip Technology Inc.
PIC16F526 FIGURE 15-5: TYPICAL IPD vs. VDD (SLEEP MODE, ALL PERIPHERALS DISABLED) 0.45 0.40 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 0.35 IPD (A) 0.30 0.25 0.20 0.15 0.10 0.05 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) MAXIMUM IPD vs. VDD (SLEEP MODE, ALL PERIPHERALS DISABLED) FIGURE 15-6: 18.0 16.0 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 14.0 Max. 125°C IPD (A) 12.0 10.0 8.0 6.0 4.0 Max.
PIC16F526 FIGURE 15-7: TYPICAL WDT IPD vs. VDD 9 8 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 7 IPD (A) 6 5 4 3 2 1 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 15-8: MAXIMUM WDT IPD vs. VDD OVER TEMPERATURE 25.0 20.0 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) IPD (A) Max. 125°C 15.0 10.0 Max. 85°C 5.0 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) 2010 Microchip Technology Inc.
PIC16F526 FIGURE 15-9: 80 COMPARATOR IPD vs. VDD (COMPARATOR ENABLED) Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) Maximum Typical IPD (A) 60 40 20 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 15-10: WDT TIME-OUT vs. VDD OVER TEMPERATURE (NO PRESCALER) 50 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) Max. 125°C 45 40 Max. 85°C 35 Time (ms) 30 Typical. 25°C 25 20 Min. -40°C 15 10 5 0 2.0 2.5 3.
PIC16F526 FIGURE 15-11: VOL vs. IOL OVER TEMPERATURE (VDD = 3.0V) (VDD = 3V, -40×C TO 125×C) 0.8 0.7 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) Max. 125°C 0.6 Max. 85°C VOL (V) 0.5 0.4 Typical 25°C 0.3 0.2 Min. -40°C 0.1 0.0 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 IOL (mA) FIGURE 15-12: VOL vs. IOL OVER TEMPERATURE (VDD = 5.0V) 0.
PIC16F526 FIGURE 15-13: VOH vs. IOH OVER TEMPERATURE (VDD = 3.0V) 3.5 3.0 Max. -40°C Typ. 25°C 2.5 Min. 125°C VOH (V) 2.0 1.5 1.0 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 0.5 0.0 0.0 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 -3.5 -4.0 IOH (mA) FIGURE 15-14: (VDD = 5.0V) VOH vs. IOH OVER TEMPERATURE ( , ) 5.5 5.0 Max. -40°C Typ. 25°C VOH (V) 4.5 Min. 125°C 4.0 3.
PIC16F526 FIGURE 15-15: TTL INPUT THRESHOLD VIN vs. VDD (TTL Input, -40×C TO 125×C) 1.7 1.5 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) Max. -40°C VIN (V) 1.3 Typ. 25°C 1.1 Min. 125°C 0.9 0.7 0.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 15-16: SCHMITT TRIGGER INPUT THRESHOLD VIN vs. VDD (ST Input, -40×C TO 125×C) 4.0 VIH Max. 125°C 3.5 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) VIH Min.
PIC16F526 FIGURE 15-17: DEVICE RESET TIMER (HS, XT AND LP) vs. VDD Maximum (Sleep Mode all Peripherals Disabled) 45 40 35 Max. 125°C DRT (ms) 30 25 Max. 85°C 20 Typical. 25°C 15 Min. -40°C 10 5 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) Note: See Table 14-9 if another clock mode is selected. DS41326E-page 106 2010 Microchip Technology Inc.
PIC16F526 16.0 PACKAGING INFORMATION 16.1 Package Marking Information 14-Lead PDIP (300 mil) Example XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN PIC16F526 -I/PG e3 0215 0410017 Example 14-Lead SOIC (3.90 mm) PIC16F526-E /SLG0125 0431017 XXXXXXXXXXX XXXXXXXXXXX YYWWNNN Example 14-Lead TSSOP (4.
PIC16F526 /HDG 3ODVWLF 'XDO ,Q /LQH 3 ± PLO %RG\ >3',3@ 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ N NOTE 1 E1 1 3 2 D E A2 A L A1 c b1 b e eB 8QLWV 'LPHQVLRQ /LPLWV 1XPEHU RI 3LQV ,1&+(6 0,1 1 120 0$; 3LWFK H 7RS WR 6HDWLQJ 3ODQH $ ± ± 0ROGHG 3DFNDJH 7KLFNQHVV $ %DVH WR 6HDWLQJ 3ODQH $ ± ± 6KRXOGHU WR 6KRXOGHU :LGWK (
PIC16F526 /HDG 3ODVWLF 6PDOO 2XWOLQH 6/ ± 1DUURZ PP %RG\ >62,&@ 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ D N E E1 NOTE 1 1 2 3 e h b α h A A2 c φ L A1 β L1 8QLWV 'LPHQVLRQ /LPLWV 1XPEHU RI 3LQV 0,//,0(7(56 0,1 1 120 0$; 3LWFK H 2YHUDOO +HLJKW $ ± %6& ± 0ROGHG 3DFNDJH 7KLFNQHVV $ ± ± 6WDQGRII $ ± 2YHUDOO :LGWK ( 0ROGHG 3DFNDJH :LGW
PIC16F526 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ DS41326E-page 110 2010 Microchip Technology Inc.
PIC16F526 /HDG 3ODVWLF 7KLQ 6KULQN 6PDOO 2XWOLQH 67 ± PP %RG\ >76623@ 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ D N E E1 NOTE 1 1 2 e b c φ A2 A A1 8QLWV 'LPHQVLRQ /LPLWV 1XPEHU RI 3LQV L L1 0,//,0(7(56 0,1 1 120 0$; 3LWFK H 2YHUDOO +HLJKW $ ± %6& ± 0ROGHG 3DFNDJH 7KLFNQHVV $ 6WDQGRII $ ± 2YHUDOO :LGWK ( 0ROGHG 3DFNDJH :LGWK (
PIC16F526 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS41326E-page 112 2010 Microchip Technology Inc.
PIC16F526 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2010 Microchip Technology Inc.
PIC16F526 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS41326E-page 114 2010 Microchip Technology Inc.
PIC16F526 APPENDIX A: REVISION HISTORY Revision A (August 2007) Original release of this document. Revision B (December 2008) Added DC and AC Characteristics graphs; Updated Electrical Characteristics section; added I/O diagrams; updated the Flash Data Memory Control Section; made various changes to the Special Features of the CPU Section and made general edits. Miscellaneous updates.
PIC16F526 NOTES: DS41326E-page 116 2010 Microchip Technology Inc.
PIC16F526 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers.
PIC16F526 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document.
PIC16F526 INDEX A A/D Specifications.............................................................. 89 ALU ..................................................................................... 11 Assembler MPASM Assembler..................................................... 80 B Block Diagram Comparator for the PIC16F526................................... 65 On-Chip Reset Circuit ................................................. 51 Timer0......................................................................
PIC16F526 W Wake-up from Sleep ........................................................... 56 Watchdog Timer (WDT) ................................................ 43, 53 Period.......................................................................... 53 Programming Considerations ..................................... 53 WWW Address.................................................................. 115 WWW, On-Line Support........................................................ 5 Z Zero bit ................
PIC16F526 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX XXX Device Temperature Range Package Pattern Examples: a) b) Device: PIC16F526 PIC16F526T(1) Temperature Range: I E = = Package: P SL ST MG Pattern: Special Requirements c) d) PIC16F526-E/P 301 = Extended Temp., PDIP package, QTP pattern #301 PIC16F526-I/SL = Industrial Temp., SOIC package PIC16F526T-E/P = Extended Temp.
WORLDWIDE SALES AND SERVICE AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Web Address: www.microchip.
