Datasheet

© 2007 Microchip Technology Inc. DS41268D-page 93
PIC12F510/16F506
TABLE 13-6: TIMING REQUIREMENTS
FIGURE 13-8: RESET, WATCHDOG TIMER AND DEVICE RESET TIMER TIMING
AC CHARACTERISTICS
Standard Operating Conditions (unless otherwise specified)
Operating Temperature -40°C ≤ TA ≤ +85°C (industrial)
-40°C ≤ T
A ≤ +125°C (extended)
Param
No.
Sym Characteristic Min Typ
(1)
Max Units
17 T
OSH2IOVOSC1↑ (Q1 cycle) to Port out valid
(2), (3)
— — 100* ns
18 TOSH2IOIOSC1↑ (Q2 cycle) to Port input invalid
(I/O in hold time)
(2)
50 — — ns
19 T
IOV2OSH Port input valid to OSC1↑ (I/O in setup time) 20 — — ns
20 TIOR Port output rise time
(2), (3)
— 10 25** ns
21 T
IOF Port output fall time
(2), (3)
— 10 25** ns
* These parameters are characterized but not tested.
** These parameters are design targets and are not tested.
Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design
guidance only and are not tested.
2: Measurements are taken in EXTRC mode.
3: See Figure 13-5 for loading conditions.
VDD
MCLR
Internal
POR
DRT
Timeout
(2)
Internal
Reset
Watchdog
Timer Reset
32
31
34
I/O pin
(1)
32
32
34
30
Note 1: I/O pins must be taken out of High-Impedance mode by enabling the output drivers in software.
2: Runs in MCLR
or WDT Reset only in XT, LP and HS modes.