Datasheet

PIC12F510/16F506

(1)

— — — — — — — —

bit 15 bit 8

— — IOSCFS MCLRE CP WDTE FOSC1 FOSC0

bit 7 bit 0

bit 15-6 Unimplemented: Read as ‘1’

bit 5 IOSCFS: Internal Oscillator Frequency Select bit

1 = 8 MHz INTOSC speed

0 = 4 MHz INTOSC speed

bit 4 MCLRE: Master Clear Enable bit

1 = GP3/MCLR

pin functions as MCLR

0 = GP3/MCLR pin functions as GP3, MCLR internally tied to VDD

bit 3 CP: Code Protection bit

1 = Code protection off

0 = Code protection on

bit 2 WDTE: Watchdog Timer Enable bit

1 = WDT enabled

0 = WDT disabled

bit 1-0 FOSC<1:0>: Oscillator Selection bits

00 = LP oscillator with 18 ms DRT

01 = XT oscillator with 18 ms DRT

10 = INTOSC with 1.125 ms DRT

(2)

11 = EXTRC with 1.125 ms DRT

(2)

Note 1: Refer to the “PIC12F510 Memory Programming Specification” (DS41257) to determine how to access the

Configuration Word.

2: It is the responsibility of the application designer to ensure the use of the 1.125 ms (nominal) DRT will

result in acceptable operation. Refer to Electrical Specifications for V

DD rise time and stability require-

ments for this mode of operation.