Datasheet

© 2007 Microchip Technology Inc. DS41268D-page 53
PIC12F510/16F506
9.1.6 ANALOG CONVERSION RESULT
REGISTER
The ADRES register contains the results of the last
conversion. These results are present during the sam-
pling period of the next analog conversion process.
After the sampling period is over, ADRES is cleared
(= 0). A ‘leading one’ is then right shifted into the
ADRES to serve as an internal conversion complete
bit. As each bit weight, starting with the MSB, is con-
verted, the leading one is shifted right and the con-
verted bit is stuffed into ADRES. After a total of 9 right
shifts of the ‘leading one’ have taken place, the conver-
sion is complete; the ‘leading one’ has been shifted out
and the GO/DONE
bit is cleared.
If the GO/DONE
bit is cleared in software during a con-
version, the conversion stops. The data in ADRES is
the partial conversion result. This data is valid for the bit
weights that have been converted. The position of the
‘leading one’ determines the number of bits that have
been converted. The bits that were not converted
before the GO/DONE
was cleared are unrecoverable.
REGISTER 9-1: ADCON0: A/D CONTROL REGISTER (PIC12F510)
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0
ANS1 ANS0 ADCS1 ADCS0 CHS1 CHS0 GO/DONE ADON
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-6 ANS<1:0>: ADC Analog Input Pin Select bits
(1), (2)
00 = No pins configured for analog input
01 = AN2 configured as an analog input
10 = AN2 and AN0 configured as analog inputs
11 = AN2, AN1 and AN0 configured as analog inputs
bit 5-4 ADCS<1:0>: ADC Conversion Clock Select bits
00 = FOSC/16
01 = F
OSC/8
10 = F
OSC/4
11 = INTOSC/4
bit 3-2 CHS<1:0>: ADC Channel Select bits
00 = Channel AN0
01 = Channel AN1
10 = Channel AN2
11 = 0.6V absolute voltage reference
bit 1 GO/DONE
: ADC Conversion Status bit
(4)
1 = ADC conversion in progress. Setting this bit starts an ADC conversion cycle. This bit is
automatically cleared by hardware when the ADC is done converting.
0 = ADC conversion completed/not in progress. Manually clearing this bit while a conversion is in
process terminates the current conversion.
bit 0 ADON: ADC Enable bit
1 = ADC module is operating
0 = ADC module is shut-off and consumes no power
Note 1: When the ANS bits are set, the channels selected will automatically be forced into Analog mode, regard-
less of the pin function previously defined. The only exception to this is the comparator, where the analog
input to the comparator and the ADC will be active at the same time. It is the users responsibility to ensure
that the ADC loading on the comparator input does not affect their application.
2: The ANS<1:0> bits are active regardless of the condition of ADON.
3: CHS<1:0> bits default to 11 after any Reset.
4: If the ADON bit is clear, the GO/DONE bit cannot be set.