Datasheet

PIC12F510/16F506
DS41268D-page 52 © 2007 Microchip Technology Inc.
9.1.5 SLEEP
This ADC does not have a dedicated ADC clock, and
therefore, no conversion in Sleep is possible. If a
conversion is underway and a Sleep command is
executed, the GO/DONE
and ADON bit will be cleared.
This will stop any conversion in process and power-
down the ADC module to conserve power. Due to the
nature of the conversion process, the ADRES may con-
tain a partial conversion. At least 1 bit must have been
converted prior to Sleep to have partial conversion data
in ADRES. The ADCS and CHS bits are reset to their
default condition; ANS<1:0> = 11 and CHS<1:0> = 11.
• For accurate conversions, T
AD must meet the
following:
•500ns < T
AD < 50 μs
•TAD = 1/(FOSC/divisor)
Shaded areas indicate T
AD out of range for accurate
conversions. If analog input is desired at these
frequencies, use INTOSC/4 for the ADC clock source.
TABLE 9-2: TAD FOR ADCS SETTINGS WITH VARIOUS OSCILLATORS
Note 1: When operating with external oscillator frequencies of 16 MHz or higher, better ADC performance will result
from selection of a suitable F
OSC divisor value from Table 9-2 than from use of the INTOSC/4 option for the
ADC clock.
TABLE 9-3: EFFECTS OF SLEEP ON ADCON0
Source
ADCS
<1:0>
Divisor
20
(1)
MHz
16
(1)
MHz
8MHz 4MHz 1MHz
500
kHz
350
kHz
200
kHz
100
kHz
32 kHz
INTOSC 11 4
— —.5μs1μs — — — — — —
FOSC 10 4 .2 μs .25 μs.5μs1μs4μs8μs11μs20μs40μs 125 μs
FOSC 01 8
.4 μs.5μs1μs2μs8μs16μs23μs40μs 80 μs 250 μs
FOSC 00 16 .8 μs1μs2μs4μs16μs32μs46μs 80 μs 160 μs 500 μs
ANS1 ANS0 ADCS1 ADCS0 CHS1 CHS0 GO/DONE ADON
Entering
Sleep
Unchanged Unchanged 111100
Wake or
Reset
11111100