Datasheet

© 2007 Microchip Technology Inc. DS41268D-page 39
PIC12F510/16F506
6.0 TMR0 MODULE AND TMR0
REGISTER
The Timer0 module has the following features:
• 8-bit timer/counter register, TMR0
• Readable and writable
• 8-bit software programmable prescaler
• Internal or external clock select:
- Edge select for external clock
- External clock from either the T0CKI pin or
from the output of the comparator
Figure 6-1 is a simplified block diagram of the Timer0
module.
Timer mode is selected by clearing the T0CS bit
(OPTION<5>). In Timer mode, the Timer0 module will
increment every instruction cycle (without prescaler). If
TMR0 register is written, the increment is inhibited for
the following two cycles (Figure 6-2 and Figure 6-3).
The user can work around this by writing an adjusted
value to the TMR0 register.
There are two types of Counter mode. The first Counter
mode uses the T0CKI pin to increment Timer0. It is
selected by setting the T0CKI bit (OPTION<5>), setting
the C
1T0CS bit (CM1CON0<4>) and setting the
C
1OUTEN bit (CM1CON0<6>). In this mode, Timer0
will increment either on every rising or falling edge of
pin T0CKI. The T0SE bit (OPTION<4>) determines the
source edge. Clearing the T0SE bit selects the rising
edge. Restrictions on the external clock input are
discussed in detail in Section 6.1 “Using Timer0 With
An External Clock”.
The second Counter mode uses the output of the com-
parator to increment Timer0. It can be entered in two
different ways. The first way is selected by setting the
T0CS bit (OPTION<5>), and clearing the C1T0CS
bit
(CM1CON0<4>) (C1OUTEN
[CM1CON0<6>] does not
affect this mode of operation). This enables an internal
connection between the comparator and the Timer0.
The second way is selected by setting the T0CS bit
(OPTION<5>), setting the C1T0CS
bit (CM1CON0)
and clearing the C1OUTEN
bit (CM1CON0<6>). This
allows the output of the comparator onto the T0CKI pin,
while keeping the T0CKI input active. Therefore, any
comparator change on the COUT pin is fed back into
the T0CKI input. The T0SE bit (OPTION<4>) deter-
mines the source edge. Clearing the T0SE bit selects
the rising edge. Restrictions on the external clock input
as discussed in Section 6.1 “Using Timer0 With An
External Clock”.
The prescaler may be used by either the Timer0
module or the Watchdog Timer, but not both. The
prescaler assignment is controlled in software by the
control bit PSA (OPTION<3>). Clearing the PSA bit will
assign the prescaler to Timer0. The prescaler is not
readable or writable. When the prescaler is assigned to
the Timer0 module, prescale values of 1:2, 1:4,...,
1:256 are selectable. Section 6.2 “Prescaler” details
the operation of the prescaler.
A summary of registers associated with the Timer0
module is found in Table 6-1.
FIGURE 6-1: TIMER0 BLOCK DIAGRAM
Note 1: Bits T0CS, T0SE, PSA, PS2, PS1 and PS0 are located in the OPTION register.
2: The prescaler is shared with the Watchdog Timer (Figure 6-5).
3: Bit C1T0CS
is located in the CM1CON0 register, CM1CON0<4>.
0
1
1
0
T0CS
(1)
FOSC/4
Programmable
Prescaler
(2)
Sync with
Internal
Clocks
TMR0 Reg
PSOUT
(2 TCY delay)
PS
OUT
Data Bus
8
PSA
(1)
PS2, PS1, PS0
(1)
3
Sync
T0SE
(1)
T0CKI
Pin
C1T0CS
(3)
1
0
Internal
Comparator
Output