Datasheet

© 2007 Microchip Technology Inc. DS41268D-page 35
PIC12F510/16F506
TABLE 5-5: REQUIREMENTS FOR DIGITAL PIN OPERATION (PIC12F510)
GP0 GP0 GP1 GP1 GP2 GP2 GP3 GP4 GP5
CM1CON0
C1ON 01 0 101
C1PREF 0 1
C1NREF 0
C1T0CS 1
C1OUTEN
1
CM2CON0
C2ON
C2PREF1
C2PREF2
C2NREF
C2OUTEN
VRCON0
VROE
VREN
OPTION
T0CS
0
ADCON0
ANS<1:0> 00, 01 00, 01 00, 01, 10 00, 01, 10 00 00
CONFIG
MCLRE
INTOSC
LP
Disabled Disabled
EXTRC —Disabled
XT Disabled Disabled
Note 1: Multiple column entries for a pin demonstrate the different permutations to arrive at digital functionality for
the pin.
2: Shaded cells indicate the bit status does not affect the pins digital functionality.