Datasheet

PIC12F510/16F506
DS41268D-page 28 © 2007 Microchip Technology Inc.
FIGURE 5-2: BLOCK DIAGRAM OF
GP0/RB0 AND GP1/RB1
FIGURE 5-3: BLOCK DIAGRAM OF
GP3/RB3 (With Weak
Pull-up And Wake-up On
Change)
Data
Bus
QD
Q
CK
QD
Q
CK
WR
Port
TRIS ‘f’
Data
TRIS
RD Port
W
Reg
Latch
Latch
Reset
Note 1: I/O pins have protection diodes to VDD and
V
SS.
D
CK
Q
Mismatch
RBPU
GPPU
ADC pin Ebl
COMP pin Ebl
ADC
COMP
I/O Pin
(1)
Data Bus
RD Port
Note 1: GP3/MCLR pin has a protection diode to VSS
only.
GPPU
D
CK
Q
Mismatch
MCLRE
RBPU
Reset
I/O Pin
(1)