Datasheet

PIC12F510/16F506
DS41268D-page 10 © 2007 Microchip Technology Inc.
FIGURE 3-1: PIC12F510 SERIES BLOCK DIAGRAM
Flash
Program
Memory
10-11
Data Bus
8
12
Program
Bus
Instruction Reg
Program Counter
RAM
File
Registers
Direct Addr
5
RAM Addr
9
Addr MUX
Indirect
Addr
FSR Reg
STATUS Reg
MUX
ALU
W Reg
Device Reset
Power-on
Reset
Watchdog
Timer
Instruction
Decode &
Control
Timing
Generation
OSC1/CLKIN
MCLR
VDD, VSS
Timer0
GPIO
8
8
GP4
GP3
GP2
GP1/ICSPCLK
GP0/ICSPDAT
5-7
3
GP5
STACK 1
STACK 2
Internal RC
Clock
1K x 12
38 bytes
Timer
Comparator
8-bit ADC
C1IN+
C1IN-
C1OUT
AN0
AN1
AN2
CVREF
OSC2
T0CKI