PIC12F510/16F506 Data Sheet 8/14-Pin, 8-Bit Flash Microcontrollers © 2007 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
PIC12F510/16F506 8/14-Pin, 8-Bit Flash Microcontroller Devices Included In This Data Sheet: • PIC16F506 • PIC12F510 High-Performance RISC CPU: • Only 33 Single-Word Instructions to Learn • All Single-Cycle Instructions except for Program Branches, which are Two-Cycle • 12-Bit Wide Instructions • Two-Level Deep Hardware Stack • Direct, Indirect and Relative Addressing modes for Data and Instructions • 8-Bit Wide Data Path • 10 Special Function Hardware Registers (PIC12F510) • 13 Special Function Hardware Re
PIC12F510/16F506 Program Memory Data Memory Flash (words) SRAM (bytes) PIC16F506 1024 PIC12F510 1024 Device I/O Timers 8-bit 67 12 1 38 6 1 Pin Diagrams PDIP, SOIC and TSSOP VSS 12 RB1/AN1/C1IN-/ICSPCLK 11 RB2/AN2/C1OUT 10 RC0/C2IN+ 9 RC1/C2IN- 7 8 RC2/CVREF VDD 1 GP4/OSC2 2 3 8 7 VSS GP5/OSC1/CLKIN 6 GP1/AN1/C1IN-/ICSPCLK GP3/MCLR/VPP 4 5 GP2/AN2/T0CKI/C1OUT 1 2 RB4/OSC2/CLKOUT 3 RB3/MCLR/VPP RC5/T0CKI 4 5 RC4/C2OUT 6 RC3 PIC16F506 14 13 VDD RB5/OSC1/CLKI
PIC12F510/16F506 Table of Contents 1.0 General Description...................................................................................................................................................................... 5 2.0 PIC12F510/16F506 Device Varieties .......................................................................................................................................... 7 3.0 Architectural Overview ...............................................................................
PIC12F510/16F506 NOTES: DS41268D-page 4 © 2007 Microchip Technology Inc.
PIC12F510/16F506 1.0 GENERAL DESCRIPTION The PIC12F510/16F506 devices from Microchip Technology are low-cost, high-performance, 8-bit, fullystatic, Flash-based CMOS microcontrollers. They employ a RISC architecture with only 33 single-word/ single-cycle instructions. All instructions are singlecycle except for program branches, which take two cycles. The PIC12F510/16F506 devices deliver performance in an order of magnitude higher than their competitors in the same price category.
PIC12F510/16F506 NOTES: DS41268D.-page 6 © 2007 Microchip Technology Inc.
PIC12F510/16F506 2.0 PIC12F510/16F506 DEVICE VARIETIES A variety of packaging options are available. Depending on application and production requirements, the proper device option can be selected using the information in this section. When placing orders, please use the PIC12F510/16F506 Product Identification System at the back of this data sheet to specify the correct part number. 2.1 Quick Turn Programming (QTP) Devices 2.
PIC12F510/16F506 NOTES: DS41268D-page 8 © 2007 Microchip Technology Inc.
PIC12F510/16F506 3.0 ARCHITECTURAL OVERVIEW The high performance of the PIC12F510/16F506 devices can be attributed to a number of architectural features commonly found in RISC microprocessors. The PIC12F510/16F506 devices use a Harvard architecture in which program and data are accessed on separate buses. This improves bandwidth over traditional von Neumann architectures where program and data are fetched on the same bus.
PIC12F510/16F506 FIGURE 3-1: PIC12F510 SERIES BLOCK DIAGRAM 10-11 Flash 8 Data Bus Program Counter GPIO GP0/ICSPDAT GP1/ICSPCLK GP2 GP3 GP4 GP5 1K x 12 Program Bus RAM STACK 1 Program Memory 38 bytes STACK 2 File Registers 12 RAM Addr 9 Addr MUX Instruction Reg Direct Addr 5 5-7 Indirect Addr FSR Reg STATUS Reg 8 3 Device Reset Timer OSC1/CLKIN OSC2 Instruction Decode & Control Power-on Reset Timing Generation Watchdog Timer Internal RC Clock MUX ALU 8 W Reg Timer0 MCLR Comp
PIC12F510/16F506 TABLE 3-2: PIN DESCRIPTIONS – PIC12F510 Name I/O/P Type Input Type Output Type GP0/AN0/C1IN+/ICSPDAT GP0 TTL CMOS Description Bidirectional I/O port. Can be software programmed for internal weak pull-up and wake-up from Sleep on pin change. AN0 AN — ADC channel input. C1IN+ AN — Comparator input. ICSPDAT ST CMOS In-Circuit Serial Programming data pin. GP1 TTL CMOS Bidirectional I/O port.
PIC12F510/16F506 FIGURE 3-2: PIC16F506 SERIES BLOCK DIAGRAM 10 Flash 1K x 12 Program Memory PORTB RB0/ICSPDAT RB1/ICSPCLK RB2 RB3 RB4 RB5 RAM 67 bytes File Registers STACK 1 STACK 2 Program Bus 8 Data Bus Program Counter 10 RAM Addr 9 PORTC Addr MUX Instruction Reg Direct Addr 5 5-7 RC0 RC1 RC2 RC3 RC4 RC5 Indirect Addr FSR Reg STATUS Reg 8 3 Device Reset Timer OSC1/CLKIN OSC2/CLKOUT Instruction Decode & Control Power-on Reset Timing Generation Watchdog Timer Internal RC Clock Com
PIC12F510/16F506 TABLE 3-3: PIN DESCRIPTIONS – PIC16F506 Name Function Input Type Output Type RB0/AN0/C1IN+/ICSPDAT RB0 TTL CMOS Description Bidirectional I/O port. Can be software programmed for internal weak pull-up and wake-up from Sleep on pin change. AN0 AN — ADC channel input. C1IN+ AN — Comparator 1 input. ICSPDAT ST CMOS In-Circuit Serial Programming data pin. RB1 TTL CMOS Bidirectional I/O port.
PIC12F510/16F506 3.1 Clocking Scheme/Instruction Cycle 3.2 Instruction Flow/Pipelining An instruction cycle consists of four Q cycles (Q1, Q2, Q3 and Q4). The instruction fetch and execute are pipelined such that fetch takes one instruction cycle, while decode and execute take another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the PC to change (e.g.
PIC12F510/16F506 MEMORY ORGANIZATION The PIC12F510/16F506 memories are organized into program memory and data memory. For devices with more than 512 bytes of program memory, a paging scheme is used. Program memory pages are accessed using STATUS register bit PA0. For the PIC12F510 and PIC16F506, with data memory register files of more than 32 registers, a banking scheme is used. Data memory banks are accessed using the File Select Register (FSR). 4.
PIC12F510/16F506 4.2 Data Memory Organization FIGURE 4-2: Data memory is composed of registers or bytes of RAM. Therefore, data memory for a device is specified by its register file. The register file is divided into two functional groups: Special Function Registers (SFRs) and General Purpose Registers (GPRs). FSR<5> 0 1 File Address The Special Function Registers include the TMR0 register, the Program Counter (PCL), the STATUS register, the I/O registers (ports) and the File Select Register (FSR).
PIC12F510/16F506 4.2.2 SPECIAL FUNCTION REGISTERS The Special Function Registers (SFRs) are registers used by the CPU and peripheral functions to control the operation of the device (see Table 4-1). The Special Function Registers can be classified into two sets. The Special Function Registers associated with the “core” functions are described in this section. Those related to the operation of the peripheral features are described in the section for each peripheral feature.
PIC12F510/16F506 TABLE 4-2: Address N/A SPECIAL FUNCTION REGISTER SUMMARY – PIC16F506 Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Power-on Reset TRIS I/O Control Registers (TRISB, TRISC) --11 1111 N/A OPTION Contains control bits to configure Timer0 and Timer0/WDT Prescaler 1111 1111 00h INDF Uses contents of FSR to address data memory (not a physical register) xxxx xxxx 01h TMR0 Timer0 Module Register xxxx xxxx 02h(1) PCL Low Order 8 bits of PC 03h STATUS 0
PIC12F510/16F506 REGISTER 4-1: STATUS: STATUS REGISTER (PIC12F510) R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x GPWUF CWUF PA0 TO PD Z DC C bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 GPWUF: GPIO Reset bit 1 = Reset due to wake-up from Sleep on pin change 0 = After power-up or other Reset bit 6 CWUF: Comparator Reset bit 1 = Reset due to wake-up from Slee
PIC12F510/16F506 REGISTER 4-2: STATUS: STATUS REGISTER (PIC16F506) R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x RBWUF CWUF PA0 TO PD Z DC C bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 RBWUF: PORTB Reset bit 1 = Reset due to wake-up from Sleep on pin change 0 = After power-up or other Reset bit 6 CWUF: Comparator Reset bit 1 = Reset due to wake-up from Sle
PIC12F510/16F506 4.4 OPTION Register The OPTION register is a 8-bit wide, write-only register, that contains various control bits to configure the Timer0/WDT prescaler and Timer0. By executing the OPTION instruction, the contents of the W register will be transferred to the OPTION register. A Reset sets the OPTION<7:0> bits. Note 1: If TRIS bit is set to ‘0’, the wake-up on change and pull-up functions are disabled for that pin (i.e., note that TRIS overrides Option control of GPPU/RBPU and GPWU/RBWU).
PIC12F510/16F506 REGISTER 4-4: OPTION_REG: OPTION REGISTER (PIC16F506) W-1 W-1 W-1 W-1 W-1 W-1 W-1 W-1 RBWU RBPU T0CS T0SE PSA PS2 PS1 PS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 RBWU: Enable Wake-up On Pin Change bit (RB0, RB1, RB3, RB4) 1 = Disabled 0 = Enabled bit 6 RBPU: Enable Weak Pull-Ups bit (RB0, RB1, RB3, RB4) 1 = Disabled 0 = Enabled bit 5 T0CS: Timer0 Cloc
PIC12F510/16F506 4.5 OSCCAL Register The Oscillator Calibration (OSCCAL) register is used to calibrate the internal precision 4/8 MHz oscillator. It contains seven bits for calibration. Note: Erasing the device will also erase the preprogrammed internal calibration value for the internal oscillator. The calibration value must be read prior to erasing the part so it can be reprogrammed correctly later. After you move in the calibration constant, do not change the value. See Section 10.2.
PIC12F510/16F506 4.6 Program Counter 4.6.1 EFFECTS OF RESET As a program instruction is executed, the Program Counter (PC) will contain the address of the next program instruction to be executed. The PC value is increased by one every instruction cycle, unless an instruction changes the PC. The PC is set upon a Reset, which means that the PC addresses the last location in the last page (i.e., the oscillator calibration instruction).
PIC12F510/16F506 4.8 Indirect Data Addressing: INDF and FSR Registers EXAMPLE 4-1: The INDF register is not a physical register. Addressing INDF actually addresses the register whose address is contained in the FSR register (FSR is a pointer). This is indirect addressing. 4.8.
PIC12F510/16F506 FIGURE 4-6: DIRECT/INDIRECT ADDRESSING (PIC16F506) Direct Addressing Indirect Addressing (FSR) 6 5 (opcode) 4 3 2 1 0 Bank Select Location Select 6 00 01 10 00h Data Memory(1) Bank 0 Location Select Addresses map back to addresses in Bank 0. 0Fh 10h 1Fh Bank 0 Note 1: 11 (FSR) 5 4 3 2 1 3Fh Bank 1 5Fh Bank 2 7Fh Bank 3 For register map detail, see Figure 4-3. DS41268D-page 26 © 2007 Microchip Technology Inc.
PIC12F510/16F506 5.0 I/O PORT As with any other register, the I/O register(s) can be written and read under program control. However, read instructions (e.g., MOVF PORTB, W) always read the I/O pins independent of the pin’s Input/Output modes. On Reset, all I/O ports are defined as input (inputs are at high-impedance) since the I/O control registers are all set. Note: 5.1 On the PIC12F510, I/O PORTB is referenced as GPIO. On the PIC16F506, I/O PORTB is referenced as PORTB.
PIC12F510/16F506 FIGURE 5-2: BLOCK DIAGRAM OF GP0/RB0 AND GP1/RB1 FIGURE 5-3: BLOCK DIAGRAM OF GP3/RB3 (With Weak Pull-up And Wake-up On Change) GPPU RBPU GPPU RBPU Data Bus MCLRE D Q Data Latch WR Port CK I/O Pin(1) Q Reset W Reg D I/O Pin(1) Q TRIS Latch TRIS ‘f’ CK Q Data Bus Reset RD Port ADC pin Ebl Q COMP pin Ebl D CK RD Port Mismatch Q D CK Mismatch ADC COMP Note 1: I/O pins have protection diodes to VDD and VSS.
PIC12F510/16F506 FIGURE 5-4: BLOCK DIAGRAM OF GP2 C1OUT Data Bus D Q 0 1 C1OUT Data Bus WR Port Q CK D D Q TRIS ‘f’ TRIS ‘f’ Q CK I/O Pin(1) 1 Q CK C1OUTEN W Reg TRIS Latch Q 0 Data Latch C1OUTEN W Reg BLOCK DIAGRAM OF RB2 I/O Pin(1) Data Latch WR Port FIGURE 5-5: Reset D Q TRIS Latch Q CK Reset T0CS C1T0CS ADC Pin Enable ADC Pin Enable RD Port T0CKI RD Port ADC ADC Note 1: I/O pins have protection diodes to VDD and VSS. © 2007 Microchip Technology Inc.
PIC12F510/16F506 FIGURE 5-6: BLOCK DIAGRAM OF RB4 FIGURE 5-7: BLOCK DIAGRAM OF GP4 RBPU Data Bus Data Bus D WR Port Q 0 D Q Data Latch I/O pin(1) Q CK Data Latch WR Port Q CK I/O pin(1) 1 W Reg FOSC/4 W Reg D TRIS ‘f’ Q D Q TRIS Latch Q CK TRIS Latch TRIS ‘f’ Reset Q CK INTOSC/RC Reset INTOSC/RC/EC CLKOUT Enable (Note 2) RD Port OSC1 Oscillator Circuit RD Port OSC1 Note 1: 2: Oscillator Circuit I/O pins have protection diodes to VDD and VSS.
PIC12F510/16F506 FIGURE 5-8: Data Bus BLOCK DIAGRAM OF RB5/GP5 D Data Bus Q Data Latch WR Port I/O pin(1) Q CK W Reg FIGURE 5-9: D W Reg Q TRIS Latch TRIS ‘f’ Q CK WR Port TRIS ‘f’ BLOCK DIAGRAM OF RC0/RC1 D Q Data Latch I/O pin(1) Q CK D Q TRIS Latch Q CK Reset Reset (Note 2) Comp Pin Enable RD Port OSC2 Oscillator Circuit RD Port COMP2 Note 1: I/O pins have protection diodes to VDD and VSS. 2: Input mode is disabled when pin is used for oscillator.
PIC12F510/16F506 FIGURE 5-10: BLOCK DIAGRAM OF RC2 FIGURE 5-11: BLOCK DIAGRAM OF RC3 VROE Data Bus CVREF Data Bus WR Port D Q 1 I/O PIN(1) WR Port W Reg Q TRIS ‘f’ W Reg TRIS ‘f’ D D Q Data Latch Q CK 0 Data Latch CK I/O Pin(1) Q D Q TRIS Latch Q CK Reset TRIS Latch Q CK Reset RD Port RD Port COMP2 Note 1: I/O pins have protection diodes to VDD and VSS. DS41268D-page 32 Note 1: I/O pins have protection diodes to VDD and VSS. © 2007 Microchip Technology Inc.
PIC12F510/16F506 FIGURE 5-12: BLOCK DIAGRAM OF RC4 C2OUT Data Bus WR Port D Q 0 BLOCK DIAGRAM OF RC5 I/O Pin(1) 1 Data Latch Q CK FIGURE 5-13: Data Bus WR Port I/O Pin(1) D Q Data Latch Q CK C2OUTEN W Reg TRIS ‘f’ D Q TRIS Latch Q CK W Reg TRIS ‘f’ Reset D Q TRIS Latch Q CK T0CS Reset RD Port RD Port Note 1: I/O pins have protection diodes to VDD and VSS. © 2007 Microchip Technology Inc. T0CKI Note 1: I/O pins have protection diodes to VDD and VSS.
PIC12F510/16F506 TABLE 5-1: Address SUMMARY OF PORT REGISTERS Name Bit 7 Bit 6 TRISGPIO(1) Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Power-On Reset Value on All Other Resets — — I/O Control Register --11 1111 --11 1111 N/A (2) TRISB — — I/O Control Register --11 1111 --11 1111 N/A TRISC(2) — — I/O Control Register --11 1111 --11 1111 N/A OPTION (1) GPWU GPPU T0CS TOSE PSA PS2 PS1 PS0 1111 1111 1111 1111 N/A OPTION(2) RBWU RBPU T0CS TOSE PSA PS2 PS1 P
PIC12F510/16F506 TABLE 5-5: REQUIREMENTS FOR DIGITAL PIN OPERATION (PIC12F510) GP0 GP0 GP1 GP1 GP2 GP2 GP3 GP4 GP5 C1ON 0 1 0 1 0 1 — — — C1PREF — 0 — 1 — — — — — C1NREF — — — 0 — — — — — C1T0CS — — — — — 1 — — — C1OUTEN — — — — — 1 — — — C2ON — — — — — — — — — C2PREF1 — — — — — — — — — C2PREF2 — — — — — — — — — C2NREF — — — — — — — — — C2OUTEN — — — — — — — — — VROE — — — — — — — — — VREN
PIC12F510/16F506 TABLE 5-6: REQUIREMENTS FOR DIGITAL PIN OPERATION (PIC16F506 PORTB)(1), (2) RB0 RB0 RB0 RB1 RB1 RB2 RB2 RB3 RB4 RB5 CM1CON0 C1ON — 0 1 0 1 0 1 — — — C1PREF — — 0 — — — — — — — C1NREF — — — — 0 — — — — — C1T0CS — — — — — — — — — — C1OUTEN — — — — — — 1 — — — C2ON 1 — — — — — — — — — C2PREF1 0 — — — — — — — — — C2PREF2 1 — — — — — — — — — C2NREF — — — — — — — — — — C2OUTEN — — — —
PIC12F510/16F506 5.5 I/O Programming Considerations 5.5.1 BIDIRECTIONAL I/O PORTS Some instructions operate internally as read followed by write operations. For example, the BCF and BSF instructions read the entire port into the CPU, execute the bit operation and re-write the result. Caution must be used when these instructions are applied to a port where one or more pins are used as input/outputs.
PIC12F510/16F506 NOTES: DS41268D-page 38 © 2007 Microchip Technology Inc.
PIC12F510/16F506 6.0 TMR0 MODULE AND TMR0 REGISTER The second Counter mode uses the output of the comparator to increment Timer0. It can be entered in two different ways. The first way is selected by setting the T0CS bit (OPTION<5>), and clearing the C1T0CS bit (CM1CON0<4>) (C1OUTEN [CM1CON0<6>] does not affect this mode of operation). This enables an internal connection between the comparator and the Timer0.
PIC12F510/16F506 FIGURE 6-2: PC (Program Counter) TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC - 1 Instruction Fetch PC PC + 1 MOVWF TMR0 T0 Timer0 T0 + 1 PC (Program Counter) Write TMR0 executed PC + 5 PC + 6 NT0 + 1 NT0 Read TMR0 reads NT0 Read TMR0 reads NT0 Read TMR0 reads NT0 NT0 + 2 Read TMR0 Read TMR0 reads NT0 + 1 reads NT0 + 2 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3
PIC12F510/16F506 6.1 Using Timer0 With An External Clock When an external clock input is used for Timer0, it must meet certain requirements. The external clock requirement is due to internal phase clock (TOSC) synchronization. Also, there is a delay in the actual incrementing of Timer0 after synchronization. 6.1.1 EXTERNAL CLOCK SYNCHRONIZATION When no prescaler is used, the external clock input is the same as the prescaler output.
PIC12F510/16F506 6.2.1 SWITCHING PRESCALER ASSIGNMENT To change prescaler from the WDT to the Timer0 module, use the sequence shown in Example 6-2. This sequence must be used even if the WDT is disabled. A CLRWDT instruction should be executed before switching the prescaler. The prescaler assignment is fully under software control (i.e., it can be changed “on-the-fly” during program execution).
PIC12F510/16F506 7.0 COMPARATOR(S) The PIC12F510 contains one analog comparator module. The PIC16F506 contains two comparators and a comparator voltage reference.
PIC12F510/16F506 REGISTER 7-2: CM1CON0: COMPARATOR C1 CONTROL REGISTER (PIC16F506) R-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 C1OUT C1OUTEN C1POL C1T0CS C1ON C1NREF C1PREF C1WU bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 C1OUT: Comparator Output bit 1 = VIN+ > VIN0 = VIN+ < VIN- bit 6 C1OUTEN: Comparator Output Enable bit(1), (2) 1 = Output of comparator is NOT placed on
PIC12F510/16F506 REGISTER 7-3: CM2CON0: COMPARATOR C2 CONTROL REGISTER (PIC16F506) R-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 C2OUT C2OUTEN C2POL C2PREF2 C2ON C2NREF C2PREF1 C2WU bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 C2OUT: Comparator Output bit 1 = VIN+ > VIN0 = VIN+ < VIN- bit 6 C2OUTEN: Comparator Output Enable bit(1), (2) 1 = Output of comparator is NOT placed
PIC12F510/16F506 FIGURE 7-1: COMPARATOR 1 BLOCK DIAGRAM FOR PIC12F510/16F506 C1PREF To Data Bus C1IN- MUX 0 C1IN+ RD_CM1CON0 1 D C1WUF Q Q3 * RD_CM1CON0 C1NREF EN CL NRESET C1ON(1) C1WU C1OUTEN C1IN- + 0.6V (Internal Reference) MUX 1 - C1OUT C1 C1OUT 0 C1POL Note 1: When C1ON = 0, the comparator, C1, will produce a ‘0’ output to the XOR Gate.
PIC12F510/16F506 7.1 Comparator Operation A single comparator is shown in Figure 7-3 along with the relationship between the analog input levels and the digital output. When the analog input at VIN+ is less than the analog input VIN-, the output of the comparator is a digital low level. The shaded area of the output of the comparator in Figure 7-3 represent the uncertainty due to input offsets and response time. See Table 13-1 for Common Mode Voltage.
PIC12F510/16F506 FIGURE 7-4: ANALOG INPUT MODE VDD VT = 0.6V RS < 10 K RIC AIN CPIN 5 pF VA ILEAKAGE ±500 nA VT = 0.
PIC12F510/16F506 8.0 COMPARATOR VOLTAGE REFERENCE MODULE (PIC16F506 ONLY) 8.2 The comparator voltage reference module also allows the selection of an internally generated voltage reference for one of the C2 comparator inputs. The VRCON register (Register 8-1) controls the voltage reference module shown in Figure 8-1. 8.1 Configuring The Voltage Reference The voltage reference can output 32 voltage levels; 16 in a high range and 16 in a low range.
PIC12F510/16F506 FIGURE 8-1: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM 16 Stages 8R R R R R VDD 8R VRR 16-1 Analog MUX VREN CVREF to Comparator 2 Input VR<3:0> RC2/CVREF VREN VR<3:0> = 0000 VRR VROE TABLE 8-1: Add Name REGISTERS ASSOCIATED WITH COMPARATOR VOLTAGE REFERENCE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR Value on all other Resets 0Ch VRCON VREN VROE VRR — VR3 VR2 VR1 VR0 001- 1111 001- 1111 08h CM1CON0(1) C1OUT C1OUTEN C1POL C1T0CS C
PIC12F510/16F506 9.0 ANALOG-TO-DIGITAL (A/D) CONVERTER The A/D Converter allows conversion of an analog signal into an 8-bit digital signal. 9.1 Clock Divisors The ADC has 4 clock source settings ADCS<1:0>. There are 3 divisor values 16, 8 and 4. The fourth setting is INTOSC with a divisor of 4. These settings will allow a proper conversion when using an external oscillator at speeds from 20 MHz to 350 kHz.
PIC12F510/16F506 9.1.5 SLEEP This ADC does not have a dedicated ADC clock, and therefore, no conversion in Sleep is possible. If a conversion is underway and a Sleep command is executed, the GO/DONE and ADON bit will be cleared. This will stop any conversion in process and powerdown the ADC module to conserve power. Due to the nature of the conversion process, the ADRES may contain a partial conversion. At least 1 bit must have been converted prior to Sleep to have partial conversion data in ADRES.
PIC12F510/16F506 9.1.6 ANALOG CONVERSION RESULT REGISTER The ADRES register contains the results of the last conversion. These results are present during the sampling period of the next analog conversion process. After the sampling period is over, ADRES is cleared (= 0). A ‘leading one’ is then right shifted into the ADRES to serve as an internal conversion complete bit. As each bit weight, starting with the MSB, is converted, the leading one is shifted right and the converted bit is stuffed into ADRES.
PIC12F510/16F506 REGISTER 9-2: ADRES REGISTER R-X R-X R-X R-X R-X R-X R-X R-X ADRES7 ADRES6 ADRES5 ADRES4 ADRES3 ADRES2 ADRES1 ADRES0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared EXAMPLE 9-1: PERFORMING AN ANALOG-TO-DIGITAL CONVERSION EXAMPLE 9-2: ;Sample code operates out of BANK0 loop0 MOVLW 0xF1 ;configure A/D MOVWF ADCON0 BSF ADCON0, 1 ;start conversion BTFSC ADCON0, 1;wait
PIC12F510/16F506 10.0 SPECIAL FEATURES OF THE CPU What sets a microcontroller apart from other processors are special circuits that deal with the needs of realtime applications. The PIC12F510/16F506 microcontrollers have a host of such features intended to maximize system reliability, minimize cost through elimination of external components, provide powersaving operating modes and offer code protection. These features are: 10.
PIC12F510/16F506 REGISTER 10-1: — CONFIG: CONFIGURATION WORD REGISTER (PIC12F510)(1) — — — — — — bit 15 — bit 8 — — IOSCFS MCLRE CP WDTE bit 7 FOSC1 FOSC0 bit 0 bit 15-6 Unimplemented: Read as ‘1’ bit 5 IOSCFS: Internal Oscillator Frequency Select bit 1 = 8 MHz INTOSC speed 0 = 4 MHz INTOSC speed bit 4 MCLRE: Master Clear Enable bit 1 = GP3/MCLR pin functions as MCLR 0 = GP3/MCLR pin functions as GP3, MCLR internally tied to VDD bit 3 CP: Code Protection bit 1 = Code protection off
PIC12F510/16F506 REGISTER 10-2: — CONFIG: CONFIGURATION WORD REGISTER (PIC16F506)(1) — — — — — — — bit 15 bit 8 — IOSCFS MCLRE CP WDTE FOSC2 FOSC1 bit 7 FOSC0 bit 0 bit 11-7 Unimplemented: Read as ‘1’ bit 6 IOSCFS: Internal Oscillator Frequency Select bit 1 = 8 MHz INTOSC speed 0 = 4 MHz INTOSC speed bit 5 MCLRE: Master Clear Enable bit 1 = RB3/MCLR pin functions as MCLR 0 = RB3/MCLR pin functions as RB3, MCLR tied internally to VDD bit 4 CP: Code Protection bit 1 = Code protection
PIC12F510/16F506 10.2 10.2.1 Oscillator Configurations FIGURE 10-1: OSCILLATOR TYPES The PIC12F510/16F506 devices can be operated in up to six different oscillator modes. The user can program up to three Configuration bits (FOSC<1:0> [PIC12F510], FOSC<2:0> [PIC16F506]).
PIC12F510/16F506 TABLE 10-2: CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR – PIC12F510/16F506(2) Osc. Type Resonator Freq. Cap.Range C1 Cap. Range C2 LP 32 kHz(1) 15 pF 15 pF XT 200 kHz 1 MHz 4 MHz 47-68 pF 15 pF 15 pF 47-68 pF 15 pF 15 pF 20 MHz 15-47 pF 15-47 pF HS(3) Note 1: 2: 3: 10.2.3 For VDD > 4.5V, C1 = C2 ≈ 30 pF is recommended. These values are for design guidance only. Rs may be required to avoid overdriving crystals beyond the drive level specification.
PIC12F510/16F506 Although the oscillator will operate with no external capacitor (CEXT = 0 pF), we recommend using values above 20 pF for noise and stability reasons. With no capacitance or small external capacitance, the oscillation frequency can vary dramatically due to changes in external capacitances, such as PCB trace capacitance or package lead frame capacitance. Section 13.0 “Electrical Characteristics”, shows RC frequency variation from part-to-part due to normal process variation.
PIC12F510/16F506 10.3 Reset The device differentiates between various kinds of Reset: • • • • • • • Power-on Reset (POR) MCLR Reset during normal operation MCLR Reset during Sleep WDT Time-out Reset during normal operation WDT Time-out Reset during Sleep Wake-up from Sleep Reset on pin change Wake-up from Sleep Reset on comparator change Some registers are not reset in any way, they are unknown on POR and unchanged in any other Reset.
PIC12F510/16F506 TABLE 10-4: RESET CONDITIONS FOR REGISTERS – PIC16F506 Register Address W — Power-on Reset MCLR Reset, WDT Time-out, Wake-up On Pin Change, Wake-up on Comparator Change qqqq qqqu(1) qqqq qqqu(1) INDF 00h xxxx xxxx uuuu uuuu TMR0 01h xxxx xxxx uuuu uuuu PCL 02h 1111 1111 1111 1111 STATUS 03h 0001 1xxx 10uq quuu(2) FSR 04h 100x xxxx 10uu uuuu OSCCAL 05h 1111 111- uuuu uuu- PORTB 06h --xx xxxx --uu uuuu PORTC 07h --xx xxxx --uu uuuu CM1CON0 08h 1111
PIC12F510/16F506 10.3.1 MCLR ENABLE This Configuration bit, when unprogrammed (left in the ‘1’ state), enables the external MCLR function. When programmed, the MCLR function is tied to the internal VDD and the pin is assigned to be a I/O. See Figure 10-6. FIGURE 10-6: MCLR SELECT GPWU/RBWU (GP3/RB3)/MCLR/VPP Internal MCLR MCLRE 10.
PIC12F510/16F506 FIGURE 10-7: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT VDD Power-up Detect POR (Power-on Reset) (GP3/RB3)/MCLR/VPP MCLR Reset S Q R Q MCLRE WDT Time-out Pin Change Sleep WDT Reset Start-up Timer (10 ms, 1.
PIC12F510/16F506 FIGURE 10-10: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): SLOW VDD RISE TIME V1 VDD MCLR Internal POR TDRT DRT Time-out Internal Reset Note: When VDD rises slowly, the TDRT time-out expires long before VDD has reached its final value. In this example, the chip will reset properly if, and only if, V1 ≥ VDD min. © 2007 Microchip Technology Inc.
PIC12F510/16F506 10.5 Device Reset Timer (DRT) On the PIC12F510/16F506 devices, the DRT runs any time the device is powered up. DRT runs from Reset and varies based on oscillator selection and Reset type (see Table 10-6). The DRT operates from a free running on-chip oscillator that is separate from INTOSC. The processor is kept in Reset as long as the DRT is active. The DRT delay allows VDD to rise above VDD minimum and for the oscillator to stabilize.
PIC12F510/16F506 FIGURE 10-11: WATCHDOG TIMER BLOCK DIAGRAM From Timer0 Clock Source (Figure 6-5) 0 Watchdog Timer 1 M U X Postscaler 8-to-1 MUX PS<2:0> PSA WDTE To Timer0 (Figure 6-4) 0 1 MUX PSA WDT Time-out Note 1: TABLE 10-7: Address T0CS, T0SE, PSA, PS<2:0> are bits in the OPTION register.
PIC12F510/16F506 10.7 Time-out Sequence, Power-down and Wake-up from Sleep Status Bits (TO, PD, GPWUF/RBWUF) FIGURE 10-13: VDD VDD The TO, PD and (GPWUF/RBWUF) bits in the STATUS register can be tested to determine if a Reset condition has been caused by a power-up condition, a MCLR or Watchdog Timer (WDT) Reset.
PIC12F510/16F506 10.9 Power-Down Mode (Sleep) A device may be powered down (Sleep) and later powered up (wake-up from Sleep Reset). 10.9.1 SLEEP The Power-Down mode is entered by executing a SLEEP instruction. If enabled, the Watchdog Timer will be cleared but keeps running, the TO bit (STATUS<4>) is set, the PD bit (STATUS<3>) is cleared and the oscillator driver is turned off.
PIC12F510/16F506 10.12 In-Circuit Serial Programming™ (ICSP™) The PIC12F510/16F506 microcontrollers can be serially programmed while in the end application circuit. This is simply done with two lines for clock and data, and three other lines for power, ground and the programming voltage. This allows customers to manufacture boards with unprogrammed devices and then program the microcontroller just before shipping the product. This also allows the most recent firmware, or a custom firmware, to be programmed.
PIC12F510/16F506 11.0 INSTRUCTION SET SUMMARY The PIC16 instruction set is highly orthogonal and is comprised of three basic categories. • Byte-oriented operations • Bit-oriented operations • Literal and control operations Each PIC16 instruction is a 12-bit word divided into an opcode, which specifies the instruction type, and one or more operands which further specify the operation of the instruction.
PIC12F510/16F506 TABLE 11-2: Mnemonic, Operands ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF INSTRUCTION SET SUMMARY Description Cycles 12-Bit Opcode MSb LSb Status Notes Affected f, d f, d f – f, d f, d f, d f, d f, d f, d f, d f – f, d f, d f, d f, d f, d 0001 11df ffff C, DC, Z 1, 2, 4 Add W and f 1 0001 01df ffff AND W with f 1 Z 2, 4 0000 011f ffff Clear f 1 Z 4 0000 0100 0000 Clear W 1 Z 0010 01df ffff Complement f 1 Z 0000 11df ffff Decremen
PIC12F510/16F506 ADDWF Add W and f BCF Bit Clear f Syntax: [ label ] ADDWF Syntax: [ label ] BCF Operands: 0 ≤ f ≤ 31 d ∈ [0,1] Operands: 0 ≤ f ≤ 31 0≤b≤7 Operation: (W) + (f) → (dest) Operation: 0 → (f) Status Affected: C, DC, Z Status Affected: None Description: Description: Bit ‘b’ in register ‘f’ is cleared. f,d Add the contents of the W register and register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’.
PIC12F510/16F506 BTFSS Bit Test f, Skip if Set CLRW Clear W Syntax: [ label ] BTFSS f,b Syntax: [ label ] CLRW Operands: 0 ≤ f ≤ 31 0≤b<7 Operands: None Operation: 00h → (W); 1→Z Operation: skip if (f) = 1 Status Affected: None Status Affected: Z Description: If bit ‘b’ in register ‘f’ is ‘1’, then the next instruction is skipped.
PIC12F510/16F506 DECF Decrement f INCF Increment f Syntax: [ label ] DECF f,d Syntax: [ label ] Operands: 0 ≤ f ≤ 31 d ∈ [0,1] Operands: 0 ≤ f ≤ 31 d ∈ [0,1] Operation: (f) – 1 → (dest) Operation: (f) + 1 → (dest) Status Affected: Z Status Affected: Z Description: Decrement register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. Description: The contents of register ‘f’ are incremented.
PIC12F510/16F506 IORWF Inclusive OR W with f MOVWF Move W to f Syntax: [ label ] Syntax: [ label ] Operands: 0 ≤ f ≤ 31 d ∈ [0,1] Operands: 0 ≤ f ≤ 31 Operation: Operation: (W).OR. (f) → (dest) (W) → (f) Status Affected: None Status Affected: Z Description: Description: Inclusive OR the W register with register ‘f’. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is placed back in register ‘f’. Move data from the W register to register ‘f’.
PIC12F510/16F506 RETLW Return with Literal in W SLEEP Enter SLEEP Mode Syntax: [ label ] Syntax: [label ] Operands: 0 ≤ k ≤ 255 Operands: None Operation: k → (W); TOS → PC Operation: Status Affected: None Description: The W register is loaded with the eight-bit literal ‘k’. The program counter is loaded from the top of the stack (the return address). This is a two-cycle instruction.
PIC12F510/16F506 TRIS Load TRIS Register XORWF Exclusive OR W with f Syntax: [ label ] XORWF Operands: 0 ≤ f ≤ 31 d ∈ [0,1] Syntax: [ label ] TRIS Operands: f=6 f Operation: (W) → TRIS register f Status Affected: None Operation: (W) .XOR. (f) → (dest) Description: TRIS register ‘f’ (f = 6 or 7) is loaded with the contents of the W register Status Affected: Z Description: Exclusive OR the contents of the W register with register ‘f’.
PIC12F510/16F506 12.
PIC12F510/16F506 12.2 MPASM Assembler The MPASM Assembler is a full-featured, universal macro assembler for all PIC MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel® standard HEX files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging.
PIC12F510/16F506 12.7 MPLAB ICE 2000 High-Performance In-Circuit Emulator The MPLAB ICE 2000 In-Circuit Emulator is intended to provide the product development engineer with a complete microcontroller design tool set for PIC microcontrollers. Software control of the MPLAB ICE 2000 In-Circuit Emulator is advanced by the MPLAB Integrated Development Environment, which allows editing, building, downloading and source debugging from a single environment.
PIC12F510/16F506 12.11 PICSTART Plus Development Programmer 12.13 Demonstration, Development and Evaluation Boards The PICSTART Plus Development Programmer is an easy-to-use, low-cost, prototype programmer. It connects to the PC via a COM (RS-232) port. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. The PICSTART Plus Development Programmer supports most PIC devices in DIP packages up to 40 pins.
PIC12F510/16F506 13.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings† Ambient temperature under bias.......................................................................................................... -40°C to +125°C Storage temperature ............................................................................................................................ -65°C to +150°C Voltage on VDD with respect to VSS ......................................................................................
PIC12F510/16F506 VOLTAGE-FREQUENCY GRAPH, -40°C ≤ TA ≤ +125°C (PIC12F510) FIGURE 13-1: 6.0 5.5 5.0 VDD (Volts) 4.5 4.0 3.5 3.0 2.5 2.0 0 4 10 8 20 25 Frequency (MHz) FIGURE 13-2: MAXIMUM OSCILLATOR FREQUENCY TABLE (PIC12F510) Oscillator Mode LP XT EXTRC INTOSC 0 200 kHz 4 MHz 8 MHz 20 MHz Frequency (MHz) DS41268D-page 84 © 2007 Microchip Technology Inc.
PIC12F510/16F506 VOLTAGE FREQUENCY GRAPH, -40°C ≤ TA ≤ +125°C (PIC16F506) FIGURE 13-3: 6.0 5.5 5.0 VDD (Volts) 4.5 4.0 3.5 3.0 2.5 2.0 0 4 10 8 20 25 Frequency (MHz) FIGURE 13-4: MAXIMUM OSCILLATOR FREQUENCY TABLE (PIC16F506) Oscillator Mode LP XT EXTRC INTOSC EC HS 0 200 kHz 4 MHz 8 MHz 20 MHz Frequency (MHz) © 2007 Microchip Technology Inc.
PIC12F510/16F506 13.1 DC Characteristics: PIC12F510/16F506 (Industrial) Standard Operating Conditions (unless otherwise specified) Operating Temperature 40°C ≤ TA ≤ +85°C (industrial) DC Characteristics Param No. Sym Characteristic Min Typ(1) Max Units Conditions D001 VDD Supply Voltage 2.0 5.5 V See Figure 14-1 D002 VDR RAM Data Retention Voltage(2) — 1.5* — V Device in Sleep mode D003 VPOR VDD Start Voltage to ensure Power-on Reset — Vss — V See Section 10.
PIC12F510/16F506 13.2 DC Characteristics: PIC12F510/16F506 (Extended) Standard Operating Conditions (unless otherwise specified) Operating Temperature 40°C ≤ TA ≤ +125°C (extended) DC Characteristics Param No. Sym Characteristic Min Typ(1) Max Units Conditions D001 VDD Supply Voltage 2.0 5.5 V See Figure 14-1 D002 VDR RAM Data Retention Voltage(2) — 1.5* — V Device in Sleep mode D003 VPOR VDD Start Voltage to ensure Power-on Reset — Vss — V See Section 10.
PIC12F510/16F506 13.3 DC Characteristics: PIC12F510/16F506 (Industrial, Extended) Standard Operating Conditions (unless otherwise specified) Operating Temperature -40°C ≤ TA ≤ +85°C (industrial) -40°C ≤ TA ≤ +125°C (extended) DC CHARACTERISTICS Param No. Sym VIL Characteristic Min Typ† Max Units Conditions Input Low Voltage I/O ports D030 with TTL buffer D030A VSS — 0.8V V For 4.5 ≤ VDD ≤ 5.5V VSS — 0.15 VDD V otherwise VSS — 0.
PIC12F510/16F506 TABLE 13-1: Sym COMPARATOR SPECIFICATIONS Characteristics VOS Input Offset Voltage VCM Input Common Mode Voltage CMRR TRT VIVRF * Note 1: Common Mode Rejection Ratio Response Time(1) Internal Voltage Reference Sym * Note 1: Max Units — ±3 ±10 mV 0 — VDD – 1.5 V +55* — — dB — 150 400* ns 0.550 0.6 0.650 V Comments (VDD - 1.
PIC12F510/16F506 13.4 Timing Parameter Symbology and Load Conditions The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 2.
PIC12F510/16F506 TABLE 13-4: EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions (unless otherwise specified) Operating Temperature -40°C ≤ TA ≤ +85°C (industrial), -40°C ≤ TA ≤ +125°C (extended) AC CHARACTERISTICS Para No.
PIC12F510/16F506 TABLE 13-5: CALIBRATED INTERNAL RC FREQUENCIES AC CHARACTERISTICS Standard Operating Conditions (unless otherwise specified) Operating Temperature -40°C ≤ TA ≤ +85°C (industrial), -40°C ≤ TA ≤ +125°C (extended) Param Sym No. Freq. Min Tolerance F10 Characteristic FOSC Internal Calibrated INTOSC Frequency(1) * Note 1: Typ(1) Max* Units ±1% ±2% 7.92 7.84 8.00 8.00 8.08 8.16 ±5% 7.60 8.00 8.40 Conditions MHz VDD = 3.5V TA = 25°C MHz 2.5V ≤ VDD ≤ 5.5V 0°C ≤ TA ≤ +85°C MHz 2.
PIC12F510/16F506 TABLE 13-6: TIMING REQUIREMENTS Standard Operating Conditions (unless otherwise specified) AC CHARACTERISTICS Operating Temperature -40°C ≤ TA ≤ +85°C (industrial) -40°C ≤ TA ≤ +125°C (extended) Param No.
PIC12F510/16F506 TABLE 13-7: RESET, WATCHDOG TIMER AND DEVICE RESET TIMER Standard Operating Conditions (unless otherwise specified) Operating Temperature -40°C ≤ TA ≤ +85°C (industrial) -40°C ≤ TA ≤ +125°C (extended) AC CHARACTERISTICS Param Sym No. Characteristic 30 TMCL MCLR Pulse Width (low) 31 TWDT Watchdog Timer Time-out Period (No Prescaler) 32 TDRT Device Reset Timer Period Min Typ(1) Max Units 2000* — — ns VDD = 5.0V 9* 9* 18* 18* 30* 40* ms ms VDD = 5.
PIC12F510/16F506 TABLE 13-9: VDD (Volts) PULL-UP RESISTOR RANGES Temperature (°C) RB0 (GP0)/RB1 (GP1) 2.0 5.5 RB3 (GP3) 2.0 5.5 Min Typ Max Units -40 25 85 125 -40 25 85 125 73K 73K 82K 86K 15K 15K 19K 23K 105K 113K 123K 132k 21K 22K 26k 29K 186K 187K 190K 190K 33K 34K 35K 35K Ω Ω Ω Ω Ω Ω Ω Ω -40 25 85 125 -40 25 85 125 63K 77K 82K 86K 16K 16K 24K 26K 81K 93K 96k 100K 20k 21K 25k 27K 96K 116K 116K 119K 22K 23K 28K 29K Ω Ω Ω Ω Ω Ω Ω Ω © 2007 Microchip Technology Inc.
PIC12F510/16F506 NOTES: DS41268D-page 96 © 2007 Microchip Technology Inc.
PIC12F510/16F506 14.0 DC AND CHARACTERISTICS GRAPHS AND CHARTS. Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.
PIC12F510/16F506 FIGURE 14-2: TYPICAL IPD vs. VDD (SLEEP MODE, ALL PERIPHERALS DISABLED) Typical (Sleep Mode all Peripherals Disabled) 0.45 0.40 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) 0.35 IPD (μA) 0.30 0.25 0.20 0.15 0.10 0.05 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 14-3: MAXIMUM IPD vs. VDD (SLEEP MODE, ALL PERIPHERALS DISABLED) Maximum (Sleep Mode all Peripherals Disabled) 18.0 16.
PIC12F510/16F506 FIGURE 14-4: 80 COMPARATOR IPD vs. VDD (COMPARATOR ENABLED) Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) Maximum IPD (μA) 60 Typical 40 20 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 4.0 4.5 5.0 5.5 VDD (V) TYPICAL WDT IPD vs. VDD FIGURE 14-5: 9 8 7 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) IPD (μA) 6 5 4 3 2 1 0 2.0 2.5 3.0 3.5 VDD (V) © 2007 Microchip Technology Inc.
PIC12F510/16F506 FIGURE 14-6: MAXIMUM WDT IPD vs. VDD OVER TEMPERATURE Maximum 25.0 20.0 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) IPD (μA) Max. 125°C 15.0 10.0 Max. 85°C 5.0 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 14-7: WDT TIME-OUT vs. VDD OVER TEMPERATURE (NO PRESCALER) 50 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) Max. 125°C 45 40 Max. 85°C 35 Time (ms) 30 Typical. 25°C 25 20 Min.
PIC12F510/16F506 FIGURE 14-8: VOL vs. IOL OVER TEMPERATURE (VDD = 3.0V) (VDD = 3V, -40×C TO 125×C) 0.8 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) 0.7 Max. 125°C 0.6 VOL (V) 0.5 Max. 85°C 0.4 Typical 25°C 0.3 0.2 Min. -40°C 0.1 0.0 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 IOL (mA) FIGURE 14-9: VOL vs. IOL OVER TEMPERATURE (VDD = 5.0V) 0.
PIC12F510/16F506 FIGURE 14-10: VOH vs. IOH OVER TEMPERATURE (VDD = 3.0V) 3.5 3.0 Max. -40°C Typ. 25°C 2.5 Min. 125°C VOH (V) 2.0 1.5 1.0 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) 0.5 0.0 0.0 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 -3.5 -4.0 IOH (mA) FIGURE 14-11: (VDD = 5.0V) VOH vs. IOH OVER TEMPERATURE ( , ) 5.5 5.0 Max. -40°C Typ. 25°C VOH (V) 4.5 Min. 125°C 4.0 3.
PIC12F510/16F506 FIGURE 14-12: TTL INPUT THRESHOLD VIN vs. VDD (TTL Input, -40×C TO 125×C) 1.7 1.5 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) Max. -40°C VIN (V) 1.3 Typ. 25°C 1.1 Min. 125°C 0.9 0.7 0.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 14-13: SCHMITT TRIGGER INPUT THRESHOLD VIN vs. VDD (ST Input, -40×C TO 125×C) 4.0 VIH Max. 125°C 3.5 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) VIH Min.
PIC12F510/16F506 FIGURE 14-14: DEVICE RESET TIMER (HS, XT AND LP) vs. VDD Maximum (Sleep Mode all Peripherals Disabled) 45 40 35 Max. 125°C DRT (ms) 30 25 Max. 85°C 20 Typical 25°C 15 Min. -40°C 10 5 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) Note: See Table 13-7 if another clock mode is selected. DS41268D-page 104 © 2007 Microchip Technology Inc.
PIC12F510/16F506 15.0 PACKAGING 15.1 Package Marking Information 8-Lead PDIP Example 12F510/P 017 0410 XXXXXXXX XXXXXNNN YYWW 14-Lead PDIP Example XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN PIC16F506-I/P 0410017 8-Lead SOIC (3.90 mm) Example XXXXXXXX XXXXYYWW NNN PIC12F510-I /SN0410 017 8-Lead 2x3 DFN* Example XXX YWW NN BE0 610 17 TABLE 15-1: 8-LEAD 2X3 DFN (MC) TOP MARKING Part Number Marking PIC12F510(T)-I/MC BS0 PIC12F510-E/MC BT0 Legend: XX...
PIC12F510/16F506 15.2 Package Marking Information (Cont’d) 14-Lead SOIC (3.90 mm) XXXXXXXXXXX XXXXXXXXXXX YYWWNNN 8-Lead MSOP XXXXXX YWWNNN 14-Lead TSSOP (4.4 mm) XXXXXXXX YYWW NNN DS41268D-page 106 Example PIC16F506 -I/SL 0410017 Example 602/MS 310017 Example 16F506/ST 0410 017 © 2007 Microchip Technology Inc.
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PIC12F510/16F506 APPENDIX A: REVISION HISTORY Revision A Original release. Revision B Page 3 – Special Microcontroller Features and LowPower Features sections. PIC12F510 Pin Diagram. Section 3.0 – Figure 3-1, Figure 3-2, Table 3-2, Table 3-3. Section 4.0 – First paragraph, Section 4.2 - Figure references, Tables 4-1 and 4-2 (Note 1). Section 5.0 – Table 5-2, Table 5-6 Title. Section 6.0 Section 7.0 – First paragraph, Section 7.
PIC12F510/16F506 NOTES: DS41268D-page 116 © 2007 Microchip Technology Inc.
PIC12F510/16F506 INDEX A M ALU ....................................................................................... 9 Assembler MPASM Assembler..................................................... 80 Block Diagram Comparator for the PIC12F510................................... 46 Comparator for the PIC16F506................................... 46 On-Chip Reset Circuit ................................................. 64 Timer0.........................................................................
PIC12F510/16F506 T Timer0 Timer0 ......................................................................... 39 Timer0 (TMR0) Module ............................................... 39 TMR0 with External Clock........................................... 41 Timing Diagrams and Specifications................................... 91 Timing Parameter Symbology and Load Conditions........... 91 TRIS Registers.................................................................... 27 W Wake-up from Sleep .................
PIC12F510/16F506 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers.
PIC12F510/16F506 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document.
PIC12F510/16F506 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX XXX Device Temperature Range Package Pattern Examples: a) b) Device: c) PIC16F506 PIC12F510 PIC16F506T(1) PIC12F510T(2) PIC16F506-E/P 301 = Extended Temp., PDIP package, QTP pattern #301 PIC16F506-I/SN = Industrial Temp., SOIC package PIC16F506T-E/P = Extended Temp., PDIP package, Tape and Reel VDD range 2.0V to 5.
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