Datasheet

PIC12F508/509/16F505
DS41236B-page 48 Preliminary © 2005 Microchip Technology Inc.
FIGURE 7-11: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): SLOW VDD RISE
TIME
VDD
MCLR
Internal POR
DRT Time-out
Internal Reset
TDRT
V1
Note: When VDD rises slowly, the TDRT time-out expires long before VDD has reached its final
value. In this example, the chip will reset properly if, and only if, V1 ≥ V
DD min.