Datasheet

© 2005 Microchip Technology Inc. Preliminary DS41236B-page 47
PIC12F508/509/16F505
FIGURE 7-8: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
FIGURE 7-9: TIME-OUT SEQUENCE ON POWER-UP (MCLR
PULLED LOW)
FIGURE 7-10: TIME-OUT SEQUENCE ON POWER-UP (MCLR
TIED TO VDD): FAST VDD RISE
TIME
SQ
R
Q
VDD
(GP3/RB3)/MCLR/VPP
Power-up
Detect
POR (Power-on Reset)
WDT Reset
CHIP Reset
MCLRE
Wake-up on pin Change Reset
Start-up Timer
(10 μs or 18 ms)
WDT Time-out
Pin Change
Sleep
MCLR
Reset
VDD
MCLR
Internal POR
DRT Time-out
Internal Reset
TDRT
VDD
MCLR
Internal POR
DRT Time-out
Internal Reset
TDRT