Datasheet

© 2005 Microchip Technology Inc. Preliminary DS41236B-page 37
PIC12F508/509/16F505
FIGURE 6-5: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
(1), (2)
TCY (= FOSC/4)
Sync
2
Cycles
TMR0 Reg
8-bit Prescaler
8-to-1 MUX
M
MUX
Watchdog
Timer
PSA
0
1
0
1
WDT
Time-out
PS<2:0>
8
PSA
WDT Enable bit
0
1
0
1
Data Bus
8
PSA
T0CS
M
U
X
M
U
X
U
X
T0SE
(GP2/RC5)/T0CKI
pin
Note 1: T0CS, T0SE, PSA, PS<2:0> are bits in the OPTION register.
2: T0CKI is shared with pin RC5 on the PIC16F505 and pin GP2 on the PIC12F508/509.