Datasheet

© 2005 Microchip Technology Inc. Preliminary DS41236B-page 17
PIC12F508/509/16F505
FIGURE 4-3: PIC12F508 REGISTER
FILE MAP
FIGURE 4-4: PIC12F509 REGISTER
FILE MAP
FIGURE 4-5: PIC16F505 REGISTER FILE MAP
File Address
00h
01h
02h
03h
04h
05h
06h
07h
1Fh
INDF
(1)
TMR0
PCL
STATUS
FSR
OSCCAL
GPIO
General
Purpose
Registers
Note 1: Not a physical register. See Section 4.9
“Indirect Data Addressing: INDF and
FSR Registers”.
File Address
00h
01h
02h
03h
04h
05h
06h
07h
1Fh
INDF
(1)
TMR0
PCL
STATUS
FSR
OSCCAL
GPIO
0Fh
10h
Bank 0 Bank 1
3Fh
30h
20h
2Fh
General
Purpose
Registers
General
Purpose
Registers
General
Purpose
Registers
Addresses map
back to
addresses
in Bank 0.
Note 1: Not a physical register. See Section 4.9
“Indirect Data Addressing: INDF and FSR
Registers”.
FSR<6:5> 00 01
File Address
00h
01h
02h
03h
04h
05h
06h
07h
1Fh
INDF
(1)
TMR0
PCL
STATUS
FSR
OSCCAL
PORTB
0Fh
10h
Bank 0
Bank 1
3Fh
30h
20h
2Fh
General
Purpose
Registers
General
Purpose
Registers
General
Purpose
Registers
Addresses map back to
addresses in Bank 0.
Note 1: Not a physical register. See Section 4.9 “Indirect Data Addressing: INDF and FSR Registers”.
FSR<6:5> 00 01
Bank 3
7Fh
70h
60h
6Fh
General
Purpose
Registers
11
Bank 2
5Fh
50h
40h
4Fh
General
Purpose
Registers
10
08h
PORTC