Datasheet

PIC12F508/509/16F505
DS41236B-page 10 Preliminary © 2005 Microchip Technology Inc.
FIGURE 3-1: PIC12F508/509 BLOCK DIAGRAM
Device Reset
Timer
Power-on
Reset
Watchdog
Timer
Flash
Program
Memory
12
Data Bus
8
12
Program
Bus
Instruction Reg
Program Counter
RAM
File
Registers
Direct Addr
5
RAM Addr
9
Addr MUX
Indirect
Addr
FSR Reg
Status Reg
MUX
ALU
W Reg
Instruction
Decode &
Control
Timing
Generation
OSC1/CLKIN
OSC2
MCLR
VDD, VSS
Timer0
GPIO
8
8
GP4/OSC2
GP3/MCLR/VPP
GP2/T0CKI
GP1/ISCPCLK
GP0/ISCPDAT
5-7
3
GP5/OSC1/CLKIN
Stack 1
Stack 2
512 x 12 or
25 x 8 or
1024 x 12
4
1
x
8
Internal RC
OSC