PIC12F508/509/16F505 Data Sheet 8/14-Pin, 8-Bit Flash Microcontrollers *8-bit, 8-pin Devices Protected by Microchip’s Low Pin Count Patent: U.S. Patent No. 5,847,450. Additional U.S. and foreign patents and applications may be issued or pending. © 2005 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
PIC12F508/509/16F505 8/14-Pin, 8-Bit Flash Microcontroller Devices Included In This Data Sheet: • PIC12F508 • PIC12F509 • PIC16F505 High-Performance RISC CPU: • Only 33 single-word instructions to learn • All single-cycle instructions except for program branches, which are two-cycle • 12-bit wide instructions • 2-level deep hardware stack • Direct, Indirect and Relative Addressing modes for data and instructions • 8-bit wide data path • 8 Special Function Hardware registers • Operating speed: - DC – 20 MHz
PIC12F508/509/16F505 Pin Diagrams PDIP, SOIC, MSOP 14 VSS RB5/OSC1/CLKIN 2 13 RB0/ICSPDAT RB4/OSC2/CLKOUT 3 12 RB1/ICSPCLK RB3/MCLR/VPP 11 RB2 RC5/T0CKI 4 5 10 RC0 RC4 6 9 RC1 RC3 7 8 RC2 PIC16F505 1 VDD VDD GP5/OSC1/CLKIN 2 GP4/OSC2 3 GP3/MCLR/VPP 4 Program Memory Data Memory Flash (words) SRAM (bytes) PIC12F508 512 25 PIC12F509 1024 PIC16F505 1024 Preliminary 8 VSS 7 GP0/ICSPDAT 6 GP1/ICSPCLK 5 GP2/T0CKI I/O Timers 8-bit 6 1 41 6 1 72 12 1 D
PIC12F508/509/16F505 Table of Contents 1.0 General Description...................................................................................................................................................................... 5 2.0 PIC12F508/509/16F505 Device Varieties ................................................................................................................................... 7 3.0 Architectural Overview ..............................................................................
PIC12F508/509/16F505 NOTES: DS41236B-page 4 Preliminary © 2005 Microchip Technology Inc.
PIC12F508/509/16F505 1.0 GENERAL DESCRIPTION 1.1 The PIC12F508/509/16F505 devices from Microchip Technology are low-cost, high-performance, 8-bit, fullystatic, Flash-based CMOS microcontrollers. They employ a RISC architecture with only 33 single-word/ single-cycle instructions. All instructions are single cycle (200 μs) except for program branches, which take two cycles. The PIC12F508/509/16F505 devices deliver performance an order of magnitude higher than their competitors in the same price category.
PIC12F508/509/16F505 NOTES: DS41236B-page 6 Preliminary © 2005 Microchip Technology Inc.
PIC12F508/509/16F505 2.0 PIC12F508/509/16F505 DEVICE VARIETIES A variety of packaging options are available. Depending on application and production requirements, the proper device option can be selected using the information in this section. When placing orders, please use the PIC12F508/509/16F505 Product Identification System at the back of this data sheet to specify the correct part number. 2.1 2.
PIC12F508/509/16F505 NOTES: DS41236B-page 8 Preliminary © 2005 Microchip Technology Inc.
PIC12F508/509/16F505 3.0 ARCHITECTURAL OVERVIEW The high performance of the PIC12F508/509/16F505 devices can be attributed to a number of architectural features commonly found in RISC microprocessors. To begin with, the PIC12F508/509/16F505 devices use a Harvard architecture in which program and data are accessed on separate buses. This improves bandwidth over traditional von Neumann architectures where program and data are fetched on the same bus.
PIC12F508/509/16F505 FIGURE 3-1: PIC12F508/509 BLOCK DIAGRAM 12 Flash 512 x 12 or 1024 x 12 Program Memory 8 Data Bus Program Counter GP0/ISCPDAT GP1/ISCPCLK GP2/T0CKI GP3/MCLR/VPP GP4/OSC2 GP5/OSC1/CLKIN RAM 25 x 8 or 41 x 8 File Registers Stack 1 Stack 2 Program 12 Bus RAM Addr GPIO 9 Addr MUX Instruction Reg Direct Addr 5 5-7 Indirect Addr FSR Reg Status Reg 8 3 MUX Device Reset Timer Instruction Decode & Control OSC1/CLKIN OSC2 Timing Generation Internal RC OSC ALU Power-on Rese
PIC12F508/509/16F505 TABLE 3-2: PIC12F508/509 PINOUT DESCRIPTION Name GP0/ICSPDAT GP1\ICSPCLK GP2/T0CKI GP3/MCLR/VPP GP4/OSC2 GP5/OSC1/CLKIN Function Input Type Output Type GP0 TTL CMOS Bidirectional I/O pin. Can be software programmed for internal weak pull-up and wake-up from Sleep on pin change. ICSPDAT ST CMOS In-Circuit Serial Programming™ data pin. GP1 TTL CMOS Bidirectional I/O pin. Can be software programmed for internal weak pull-up and wake-up from Sleep on pin change.
PIC12F508/509/16F505 FIGURE 3-2: PIC16F505 BLOCK DIAGRAM 12 Flash 1K x 12 Program Memory 8 Data Bus Program Counter RB0/ICSPCLK RB1/ICSPDAT RB2 RB3/MCLR/VPP RB4/OSC2/CLKOUT RB5/OSC1/CLKIN RAM 72 bytes File Registers Stack 1 Stack 2 Program 12 Bus RAM Addr 9 PORTC Addr MUX Instruction Reg Direct Addr 5 5-7 Indirect Addr FSR Reg Status Reg 8 3 Device Reset Timer Instruction Decode & Control OSC1/CLKIN OSC2/CLKOUT Timing Generation PORTB Power-on Reset RC0 RC1 RC2 RC3 RC4 RC5/T0CKI MUX
PIC12F508/509/16F505 TABLE 3-3: PIC16F505 PINOUT DESCRIPTION Name RB0/ICSPDAT RB1/ICSPCLK Function Input Type Output Type RB0 TTL CMOS Bidirectional I/O pin. Can be software programmed for internal weak pull-up and wake-up from Sleep on pin change. ICSPDAT ST CMOS In-Circuit Serial Programming™ data pin. RB1 TTL CMOS Bidirectional I/O pin. Can be software programmed for internal weak pull-up and wake-up from Sleep on pin change. ICSPCLK ST CMOS In-Circuit Serial Programming clock pin.
PIC12F508/509/16F505 3.1 Clocking Scheme/Instruction Cycle 3.2 Instruction Flow/Pipelining An instruction cycle consists of four Q cycles (Q1, Q2, Q3 and Q4). The instruction fetch and execute are pipelined such that fetch takes one instruction cycle, while decode and execute take another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the PC to change (e.g.
PIC12F508/509/16F505 4.0 MEMORY ORGANIZATION FIGURE 4-1: The PIC12F508/509/16F505 memories are organized into program memory and data memory. For devices with more than 512 bytes of program memory, a paging scheme is used. Program memory pages are accessed using one Status register bit. For the PIC12F509 and PIC16F505, with data memory register files of more than 32 registers, a banking scheme is used. Data memory banks are accessed using the File Select Register (FSR).
PIC12F508/509/16F505 4.2 Program Memory Organization For The PIC16F505 4.3 The PIC16F505 device has a 11-bit Program Counter (PC) capable of addressing a 2K x 12 program memory space. The 1K x 12 (0000h-03FFh) for the PIC16F505 are physically implemented. Refer to Figure 4-2. Accessing a location above this boundary will cause a wraparound within the first 1K x 12 space. The effective Reset vector is at 0000h (see Figure 4-2). Location 03FFh contains the internal oscillator calibration value.
PIC12F508/509/16F505 FIGURE 4-3: PIC12F508 REGISTER FILE MAP FIGURE 4-4: PIC12F509 REGISTER FILE MAP FSR<6:5> File Address 00 01 File Address 00h INDF(1) 01h TMR0 02h PCL 03h STATUS 04h FSR 05h OSCCAL 06h GPIO 07h 00h INDF(1) 01h TMR0 02h PCL 03h STATUS 04h FSR 05h OSCCAL 06h GPIO 20h Addresses map back to addresses in Bank 0.
PIC12F508/509/16F505 4.3.2 SPECIAL FUNCTION REGISTERS The Special Function Registers (SFRs) are registers used by the CPU and peripheral functions to control the operation of the device (Table 4-1). The Special Function Registers can be classified into two sets. The Special Function Registers associated with the “core” functions are described in this section. Those related to the operation of the peripheral features are described in the section for each peripheral feature.
PIC12F508/509/16F505 TABLE 4-2: Address SPECIAL FUNCTION REGISTER (SFR) SUMMARY (PIC16F505) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Power-On Reset(2) Page # 00h INDF Uses Contents of FSR to Address Data Memory (not a physical register) xxxx xxxx 26 01h TMR0 8-bit Real-Time Clock/Counter xxxx xxxx 33 02h PCL Low-order 8 bits of PC 1111 1111 25 03h STATUS RBWUF 0-01 1xxx 20 Indirect Data Memory Address Pointer (1) 04h FSR 05h OSCCAL 06h 07h — PA0 CA
PIC12F508/509/16F505 4.4 STATUS Register This register contains the arithmetic status of the ALU, the Reset status and the page preselect bit. The STATUS register can be the destination for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable.
PIC12F508/509/16F505 REGISTER 4-2: STATUS REGISTER (ADDRESS: 03h) (PIC16F505) R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x RBWUF — PA0 TO PD Z DC C bit 7 bit 0 bit 7 RBWUF: PORTB Reset bit 1 = Reset due to wake-up from Sleep on pin change 0 = After power-up or other Reset bit 6 Reserved: Do not use bit 5 PA0: Program Page Preselect bits 1 = Page 1 (200h-3FFh) 0 = Page 0 (000h-1FFh) Each page is 512 bytes.
PIC12F508/509/16F505 4.5 OPTION Register The OPTION register is a 8-bit wide, write-only register, which contains various control bits to configure the Timer0/WDT prescaler and Timer0. Note: If TRIS bit is set to ‘0’, the wake-up on change and pull-up functions are disabled for that pin (i.e., note that TRIS overrides Option control of GPPU/RBPU and GPWU/RBWU). Note: If the T0CS bit is set to ‘1’, it will override the TRIS function on the T0CKI pin.
PIC12F508/509/16F505 REGISTER 4-4: OPTION REGISTER (PIC16F505) W-1 W-1 W-1 W-1 W-1 W-1 W-1 W-1 RBWU RBPU T0CS T0SE PSA PS2 PS1 PS0 bit 7 bit 0 bit 7 RBWU: Enable Wake-up on Pin Change bit (RB0, RB1, RB3, RB4) 1 = Disabled 0 = Enabled bit 6 RBPU: Enable Weak Pull-ups bit (RB0, RB1, RB3, RB4) 1 = Disabled 0 = Enabled bit 5 T0CS: Timer0 clock Source Select bit 1 = Transition on T0CKI pin (overrides TRIS on the T0CKI pin) 0 = Transition on internal instruction cycle clock, FOSC/4 bit 4
PIC12F508/509/16F505 4.6 OSCCAL Register The Oscillator Calibration (OSCCAL) register is used to calibrate the internal precision 4 MHz oscillator. It contains seven bits for calibration. Note: Erasing the device will also erase the preprogrammed internal calibration value for the internal oscillator. The calibration value must be read prior to erasing the part so it can be reprogrammed correctly later. After you move in the calibration constant, do not change the value. See Section 7.2.
PIC12F508/509/16F505 4.7 4.7.1 Program Counter EFFECTS OF RESET As a program instruction is executed, the Program Counter (PC) will contain the address of the next program instruction to be executed. The PC value is increased by one every instruction cycle, unless an instruction changes the PC. The PC is set upon a Reset, which means that the PC addresses the last location in the last page (i.e., the oscillator calibration instruction).
PIC12F508/509/16F505 4.9 EXAMPLE 4-1: Indirect Data Addressing: INDF and FSR Registers The INDF register is not a physical register. Addressing INDF actually addresses the register whose address is contained in the FSR register (FSR is a pointer). This is indirect addressing. 4.9.
PIC12F508/509/16F505 FIGURE 4-8: DIRECT/INDIRECT ADDRESSING (PIC16F505) Direct Addressing (FSR) 6 5 Bank Select 4 Indirect Addressing (opcode) 0 6 Location Select 01 10 00h (FSR) 0 Location Select 11 Addresses map back to addresses in Bank 0. 0Fh 10h 1Fh Bank 0 Note 1: 4 Bank 00 Data Memory(1) 5 3Fh Bank 1 5Fh Bank 2 7Fh Bank 3 For register map detail, see Section 4.3 “Data Memory Organization”. © 2005 Microchip Technology Inc.
PIC12F508/509/16F505 NOTES: DS41236B-page 28 Preliminary © 2005 Microchip Technology Inc.
PIC12F508/509/16F505 5.0 I/O PORT 5.4 As with any other register, the I/O register(s) can be written and read under program control. However, read instructions (e.g., MOVF PORTB,W) always read the I/O pins independent of the pin’s Input/Output modes. On Reset, all I/O ports are defined as input (inputs are at high-impedance) since the I/O control registers are all set. Note: 5.1 On the PIC12F508/509, I/O PORTB is referenced as GPIO. On the PIC16F505, I/O PORTB is referenced as PORTB.
PIC12F508/509/16F505 TABLE 5-1: Address SUMMARY OF PORT REGISTERS Name Bit 7 Bit 6 TRISGPIO(1) Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Power-On Reset Value on All Other Resets — — I/O Control Register --11 1111 --11 1111 N/A (2) TRISB — — I/O Control Register --11 1111 --11 1111 N/A TRISC(2) — — I/O Control Register --11 1111 --11 1111 N/A OPTION(1) GPWU GPPU TOCS TOSE PSA PS2 PS1 PS0 1111 1111 1111 1111 N/A OPTION(2) RBWU RBPU TOCS TOSE PSA PS2 PS1
PIC12F508/509/16F505 5.5 I/O Programming Considerations 5.5.1 BIDIRECTIONAL I/O PORTS Some instructions operate internally as read followed by write operations. The BCF and BSF instructions, for example, read the entire port into the CPU, execute the bit operation and re-write the result. Caution must be used when these instructions are applied to a port where one or more pins are used as input/outputs.
PIC12F508/509/16F505 NOTES: DS41236B-page 32 Preliminary © 2005 Microchip Technology Inc.
PIC12F508/509/16F505 6.0 TIMER0 MODULE AND TMR0 REGISTER Counter mode is selected by setting the T0CS bit (OPTION<5>). In this mode, Timer0 will increment either on every rising or falling edge of pin T0CKI. The T0SE bit (OPTION<4>) determines the source edge. Clearing the T0SE bit selects the rising edge. Restrictions on the external clock input are discussed in detail in Section 6.1 “Using Timer0 with an External Clock”.
PIC12F508/509/16F505 FIGURE 6-3: PC (Program Counter) TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC – 1 Instruction Fetch PC MOVWF TMR0 T0 Timer0 PC + 4 PC + 5 PC + 6 Read TMR0 reads NT0 Read TMR0 reads NT0 NT0 + 1 Read TMR0 Read TMR0 reads NT0 + 1 reads NT0 + 2 Read TMR0 reads NT0 REGISTERS ASSOCIATED WITH TIMER0 Name TMR0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 OPTION GPWU GPPU N/A
PIC12F508/509/16F505 6.1 Using Timer0 with an External Clock When an external clock input is used for Timer0, it must meet certain requirements. The external clock requirement is due to internal phase clock (TOSC) synchronization. Also, there is a delay in the actual incrementing of Timer0 after synchronization. 6.1.1 EXTERNAL CLOCK SYNCHRONIZATION When no prescaler is used, the external clock input is the same as the prescaler output.
PIC12F508/509/16F505 6.2 EXAMPLE 6-1: Prescaler An 8-bit counter is available as a prescaler for the Timer0 module or as a postscaler for the Watchdog Timer (WDT), respectively (see Section 7.6 “Watchdog Timer (WDT)”). For simplicity, this counter is being referred to as “prescaler” throughout this data sheet. Note: The prescaler may be used by either the Timer0 module or the WDT, but not both.
PIC12F508/509/16F505 BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER(1), (2) FIGURE 6-5: TCY (= FOSC/4) Data Bus 0 (GP2/RC5)/T0CKI pin 1 8 M U X 1 M U X 0 T0SE T0CS 0 Watchdog Timer 1 M U X Sync 2 Cycles TMR0 Reg PSA 8-bit Prescaler 8 8-to-1 MUX PS<2:0> PSA WDT Enable bit 1 0 MUX PSA WDT Time-out Note 1: 2: T0CS, T0SE, PSA, PS<2:0> are bits in the OPTION register. T0CKI is shared with pin RC5 on the PIC16F505 and pin GP2 on the PIC12F508/509. © 2005 Microchip Technology Inc.
PIC12F508/509/16F505 NOTES: DS41236B-page 38 Preliminary © 2005 Microchip Technology Inc.
PIC12F508/509/16F505 7.0 SPECIAL FEATURES OF THE CPU The PIC12F508/509/16F505 devices have a Watchdog Timer, which can be shut off only through configuration bit WDTE. It runs off of its own RC oscillator for added reliability. If using HS (PIC16F505), XT or LP selectable oscillator options, there is always an 18 ms (nominal) delay provided by the Device Reset Timer (DRT), intended to keep the chip in Reset until the crystal oscillator is stable.
PIC12F508/509/16F505 REGISTER 7-2: — — CONFIGURATION WORD FOR PIC16F505(1) — — — — MCLRE CP WDTE FOSC2 FOSC1 bit 11 FOSC0 bit 0 bit 11-6 Unimplemented: Read as ‘0’ bit 5 MCLRE: RB3/MCLR Pin Function Select bit 1 = RB3/MCLR pin function is MCLR 0 = RB3/MCLR pin function is digital I/O, MCLR internally tied to VDD bit 4 CP: Code Protection bit 1 = Code protection off 0 = Code protection on bit 3 WDTE: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled bit 2-0 FOSC<1:0>: Oscillato
PIC12F508/509/16F505 7.2 7.2.1 FIGURE 7-1: Oscillator Configurations OSCILLATOR TYPES The PIC12F508/509/16F505 devices can be operated in up to six different oscillator modes. The user can program up to three configuration bits (FOSC<1:0> [PIC12F508/509], FOSC<2:0> [PIC16F505]).
PIC12F508/509/16F505 TABLE 7-2: CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR – PIC12F508/509/16F505(2) Osc Type Resonator Freq. Cap. Range C1 Cap. Range C2 LP 32 kHz(1) 15 pF 15 pF XT 200 kHz 1 MHz 4 MHz 47-68 pF 15 pF 15 pF 47-68 pF 15 pF 15 pF 20 MHz 15-47 pF 15-47 pF HS(3) Note 1: 2: 3: 7.2.3 FIGURE 7-3: EXTERNAL PARALLEL RESONANT CRYSTAL OSCILLATOR CIRCUIT +5V To Other Devices 10k 74AS04 4.7k For VDD > 4.5V, C1 = C2 ≈ 30 pF is recommended. These values are for design guidance only.
PIC12F508/509/16F505 Although the oscillator will operate with no external capacitor (CEXT = 0 pF), we recommend using values above 20 pF for noise and stability reasons. With no or small external capacitance, the oscillation frequency can vary dramatically due to changes in external capacitances, such as PCB trace capacitance or package lead frame capacitance. Section 10.0 “Electrical Characteristics” shows RC frequency variation from part-to-part due to normal process variation.
PIC12F508/509/16F505 7.3 7.3.
PIC12F508/509/16F505 TABLE 7-4: RESET CONDITIONS FOR REGISTERS – PIC16F505 Register Address Power-on Reset MCLR Reset, WDT Time-out, Wake-up On Pin Change qqqq qqqu(1) qqqq qqqu(1) 00h xxxx xxxx uuuu uuuu TMR0 01h xxxx xxxx uuuu uuuu PC 02h 1111 1111 1111 1111 STATUS 03h 0001 1xxx q00q quuu(2), (3) FSR 04h 110x xxxx 11uu uuuu OSCCAL 05h 1111 111- uuuu uuu- PORTB 06h --xx xxxx --uu uuuu PORTC 07h --xx xxxx --uu uuuu OPTION — 1111 1111 1111 1111 TRISB — --11 1111
PIC12F508/509/16F505 7.3.2 MCLR ENABLE This configuration bit, when unprogrammed (left in the ‘1’ state), enables the external MCLR function. When programmed, the MCLR function is tied to the internal VDD and the pin is assigned to be a I/O. See Figure 7-7. FIGURE 7-7: MCLR SELECT GPWU/RBWU (GP3/RB3)/MCLR/VPP Internal MCLR MCLRE 7.
PIC12F508/509/16F505 FIGURE 7-8: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT VDD Power-up Detect POR (Power-on Reset) (GP3/RB3)/MCLR/VPP MCLR Reset MCLRE WDT Reset WDT Time-out S Q R Q Start-up Timer CHIP Reset (10 μs or 18 ms) Pin Change Sleep Wake-up on pin Change Reset FIGURE 7-9: TIME-OUT SEQUENCE ON POWER-UP (MCLR PULLED LOW) VDD MCLR Internal POR TDRT DRT Time-out Internal Reset TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): FAST VDD RISE TIME FIGURE 7-10: VDD MCLR Inter
PIC12F508/509/16F505 FIGURE 7-11: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): SLOW VDD RISE TIME V1 VDD MCLR Internal POR TDRT DRT Time-out Internal Reset Note: When VDD rises slowly, the TDRT time-out expires long before VDD has reached its final value. In this example, the chip will reset properly if, and only if, V1 ≥ VDD min. DS41236B-page 48 Preliminary © 2005 Microchip Technology Inc.
PIC12F508/509/16F505 7.5 TABLE 7-6: Device Reset Timer (DRT) On the PIC12F508/509/16F505 devices, the DRT runs any time the device is powered up. DRT runs from Reset and varies based on oscillator selection and Reset type (see Table 7-6). The DRT operates on an internal RC oscillator. The processor is kept in Reset as long as the DRT is active. The DRT delay allows VDD to rise above VDD min. and for the oscillator to stabilize.
PIC12F508/509/16F505 FIGURE 7-12: WATCHDOG TIMER BLOCK DIAGRAM From Timer0 Clock Source (Figure 6-5) 0 1 Watchdog Time M U X Postscaler 8-to-1 MUX PS<2:0> PSA WDT Enable Configuration Bit To Timer0 (Figure 6-4) 0 1 MUX PSA WDT Time-out Note 1: TABLE 7-7: Address T0CS, T0SE, PSA, PS<2:0> are bits in the OPTION register.
PIC12F508/509/16F505 7.7 Time-out Sequence, Power-down and Wake-up from Sleep Status Bits (TO, PD, GPWUF/RBWUF) FIGURE 7-14: VDD VDD The TO, PD and (GPWUF/RBWUF) bits in the STATUS register can be tested to determine if a Reset condition has been caused by a Power-up condition, a MCLR or Watchdog Timer (WDT) Reset.
PIC12F508/509/16F505 7.9 Power-down Mode (Sleep) 7.10 A device may be powered down (Sleep) and later powered up (wake-up from Sleep). 7.9.1 SLEEP The Power-Down mode is entered by executing a SLEEP instruction. If enabled, the Watchdog Timer will be cleared but keeps running, the TO bit (STATUS<4>) is set, the PD bit (STATUS<3>) is cleared and the oscillator driver is turned off.
PIC12F508/509/16F505 FIGURE 7-16: External Connector Signals TYPICAL IN-CIRCUIT SERIAL PROGRAMMING CONNECTION To Normal Connections PIC16F505 PIC12F508 PIC12F509 +5V VDD 0V VSS VPP MCLR/VPP CLK GP1/RB1 Data I/O GP0/RB0 VDD To Normal Connections © 2005 Microchip Technology Inc.
PIC12F508/509/16F505 NOTES: DS41236B-page 54 Preliminary © 2005 Microchip Technology Inc.
PIC12F508/509/16F505 8.0 INSTRUCTION SET SUMMARY The PIC16 instruction set is highly orthogonal and is comprised of three basic categories. • Byte-oriented operations • Bit-oriented operations • Literal and control operations Each PIC16 instruction is a 12-bit word divided into an opcode, which specifies the instruction type, and one or more operands which further specify the operation of the instruction.
PIC12F508/509/16F505 TABLE 8-2: INSTRUCTION SET SUMMARY Mnemonic, Operands ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF 12-Bit Opcode Description Cycles MSb LSb Status Notes Affected f, d f, d f — f, d f, d f, d f, d f, d f, d f, d f — f, d f, d f, d f, d f, d 0001 11df ffff C, DC, Z 1, 2, 4 Add W and f 1 0001 01df ffff AND W with f 1 Z 2, 4 0000 011f ffff Clear f 1 Z 4 0000 0100 0000 Clear W 1 Z 0010 01df ffff Complement f 1 Z 0000 11df ffff Decr
PIC12F508/509/16F505 ADDWF Add W and f BCF Syntax: [ label ] ADDWF Syntax: [ label ] BCF Operands: 0 ≤ f ≤ 31 d ∈ [0,1] Operands: 0 ≤ f ≤ 31 0≤b≤7 Operation: (W) + (f) → (dest) Operation: 0 → (f) Status Affected: C, DC, Z Status Affected: None Description: Description: Bit ‘b’ in register ‘f’ is cleared.
PIC12F508/509/16F505 BTFSS Bit Test f, Skip if Set CLRW Syntax: [ label ] BTFSS f,b Syntax: [ label ] CLRW 0 ≤ f ≤ 31 0≤b<7 Operands: None Operation: 00h → (W); 1→Z Operands: Clear W Operation: skip if (f) = 1 Status Affected: None Status Affected: Z Description: If bit ‘b’ in register ‘f’ is ‘1’, then the next instruction is skipped.
PIC12F508/509/16F505 DECF Decrement f INCF Syntax: [ label ] DECF f,d Syntax: [ label ] Operands: 0 ≤ f ≤ 31 d ∈ [0,1] Operands: 0 ≤ f ≤ 31 d ∈ [0,1] Operation: (f) – 1 → (dest) Operation: (f) + 1 → (dest) Status Affected: Z Status Affected: Z Description: Decrement register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. Description: The contents of register ‘f’ are incremented.
PIC12F508/509/16F505 IORWF Inclusive OR W with f MOVWF Syntax: [ label ] Syntax: [ label ] Operands: 0 ≤ f ≤ 31 d ∈ [0,1] Operands: 0 ≤ f ≤ 31 Operation: (W).OR. (f) → (dest) (W) → (f) Operation: Status Affected: None Status Affected: Z Description: Description: Inclusive OR the W register with register ‘f’. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is placed back in register ‘f’. Move data from the W register to register ‘f’.
PIC12F508/509/16F505 RETLW Return with Literal in W SLEEP Enter SLEEP Mode Syntax: [ label ] Syntax: [label ] Operands: 0 ≤ k ≤ 255 Operands: None Operation: k → (W); TOS → PC Operation: 00h → WDT; 0 → WDT prescaler; 1 → TO; 0 → PD Status Affected: TO, PD, RBWUF Description: Time-out Status bit (TO) is set. The Power-down Status bit (PD) is cleared. RBWUF is unaffected. The WDT and its prescaler are cleared. The processor is put into Sleep mode with the oscillator stopped. See Section 7.
PIC12F508/509/16F505 TRIS Load TRIS Register XORWF Syntax: [ label ] TRIS Syntax: [ label ] XORWF Operands: f=6 Operands: Operation: (W) → TRIS register f 0 ≤ f ≤ 31 d ∈ [0,1] f Exclusive OR W with f f,d Status Affected: None Operation: (W) .XOR. (f) → (dest) Description: TRIS register ‘f’ (f = 6 or 7) is loaded with the contents of the W register Status Affected: Z Description: Exclusive OR the contents of the W register with register ‘f’.
PIC12F508/509/16F505 9.0 DEVELOPMENT SUPPORT 9.
PIC12F508/509/16F505 9.2 MPASM Assembler 9.5 The MPASM Assembler is a full-featured, universal macro assembler for all PICmicro MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel® standard HEX files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging.
PIC12F508/509/16F505 9.7 MPLAB ICE 2000 High-Performance In-Circuit Emulator 9.9 The MPLAB ICE 2000 In-Circuit Emulator is intended to provide the product development engineer with a complete microcontroller design tool set for PICmicro microcontrollers. Software control of the MPLAB ICE 2000 In-Circuit Emulator is advanced by the MPLAB Integrated Development Environment, which allows editing, building, downloading and source debugging from a single environment.
PIC12F508/509/16F505 9.11 PICSTART Plus Development Programmer 9.12 The PICSTART Plus Development Programmer is an easy-to-use, low-cost, prototype programmer. It connects to the PC via a COM (RS-232) port. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. The PICSTART Plus Development Programmer supports most PICmicro devices in DIP packages up to 40 pins.
PIC12F508/509/16F505 10.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings(†) Ambient temperature under bias.......................................................................................................... -40°C to +125°C Storage temperature ............................................................................................................................ -65°C to +150°C Voltage on VDD with respect to VSS ................................................................................
PIC12F508/509/16F505 PIC12F508/509/16F505 VOLTAGE-FREQUENCY GRAPH, -40°C ≤ TA ≤ +125°C FIGURE 10-1: 6.0 5.5 5.0 VDD (Volts) 4.5 4.0 3.5 3.0 2.5 2.0 0 4 10 20 25 Frequency (MHz) FIGURE 10-2: MAXIMUM OSCILLATOR FREQUENCY TABLE Oscillator Mode LP XT INTOSC XTRC EC HS 0 200 kHz 4 MHz 20 MHz Frequency (MHz) DS41236B-page 68 Preliminary © 2005 Microchip Technology Inc.
PIC12F508/509/16F505 10.1 DC Characteristics: PIC12F508/509/16F505 (Industrial) DC CHARACTERISTICS Standard Operating Conditions (unless otherwise specified) Operating Temperature -40°C ≤ TA ≤ +85°C (industrial) Param No. Min Sym Characteristic Typ(1) Max Units Conditions D001 VDD Supply Voltage 2.0 5.5 V See Figure 10-1 D002 VDR RAM Data Retention Voltage(2) — 1.5* — V Device in Sleep mode D003 VPOR VDD Start Voltage to ensure Power-on Reset — VSS — V See Section 7.
PIC12F508/509/16F505 10.2 DC Characteristics: PIC12F508/509/16F505 (Extended) DC CHARACTERISTICS Param No. Sym Characteristic Standard Operating Conditions (unless otherwise specified) Operating Temperature -40°C ≤ TA ≤ +125°C (Extended) Min Typ(1) Max Units Conditions D001 VDD Supply Voltage 2.0 5.5 V See Figure 10-1 D002 VDR RAM Data Retention Voltage(2) — 1.5* — V Device in Sleep mode D003 VPOR VDD Start Voltage to ensure Power-on Reset — VSS — V See Section 7.
PIC12F508/509/16F505 DC CHARACTERISTICS: PIC12F508/509/16F505 (Industrial, Extended) TABLE 10-1: Standard Operating Conditions (unless otherwise specified) Operating temperature -40°C ≤ TA ≤ +85°C (industrial) -40°C ≤ TA ≤ +125°C (extended) Operating voltage VDD range as described in DC specification DC CHARACTERISTICS Param Sym No. VIL Characteristic Min Typ† Max Units Conditions Input Low Voltage I/O ports: D030 with TTL buffer D030A D031 with Schmitt Trigger buffer Vss — 0.
PIC12F508/509/16F505 TABLE 10-2: VDD (Volts) PULL-UP RESISTOR RANGES – PIC12F508/509/16F505 Temperature (°C) Min Typ Max Units RB0/RB1/RB4 2.0 5.5 -40 TBD TBD TBD Ω 25 TBD TBD TBD Ω 85 TBD TBD TBD Ω 125 TBD TBD TBD Ω -40 TBD TBD TBD Ω 25 TBD TBD TBD Ω 85 TBD TBD TBD Ω 125 TBD TBD TBD Ω -40 TBD TBD TBD Ω 25 TBD TBD TBD Ω 85 TBD TBD TBD Ω RB3 2.0 5.
PIC12F508/509/16F505 10.3 Timing Parameter Symbology and Load Conditions – PIC12F508/509/16F505 The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 2.
PIC12F508/509/16F505 TABLE 10-3: EXTERNAL CLOCK TIMING REQUIREMENTS – PIC12F508/509/16F505 AC CHARACTERISTICS Standard Operating Conditions (unless otherwise specified) Operating Temperature -40°C ≤ TA ≤ +85°C (industrial), -40°C ≤ TA ≤ +125°C (extended) Operating Voltage VDD range is described in Section 10.1 "DC Characteristics" Param No.
PIC12F508/509/16F505 TABLE 10-4: CALIBRATED INTERNAL RC FREQUENCIES – PIC12F508/509/16F505 AC CHARACTERISTICS Standard Operating Conditions (unless otherwise specified) Operating Temperature -40°C ≤ TA ≤ +85°C (industrial), -40°C ≤ TA ≤ +125°C (extended) Operating Voltage VDD range is described in Section 10.1 "DC Characteristics" Param No. Freq Min Tolerance F10 Sym FOSC Characteristic Internal Calibrated INTOSC Frequency(1) Typ† Max Units Conditions ± 1% 7.92 4.00 8.
PIC12F508/509/16F505 TABLE 10-5: TIMING REQUIREMENTS – PIC12F508/509/16F505 Standard Operating Conditions (unless otherwise specified) AC Operating Temperature -40°C ≤ TA ≤ +85°C (industrial) CHARACTERISTICS -40°C ≤ TA ≤ +125°C (extended) Operating Voltage VDD range is described in Section 10.1 "DC Characteristics" Param No.
PIC12F508/509/16F505 TABLE 10-6: RESET, WATCHDOG TIMER AND DEVICE RESET TIMER – PIC12F508/509/16F505 Standard Operating Conditions (unless otherwise specified) Operating Temperature -40°C ≤ TA ≤ +85°C (industrial) -40°C ≤ TA ≤ +125°C (extended) Operating Voltage VDD range is described in Section 10.1 "DC Characteristics" AC CHARACTERISTICS Param No. Max Units Conditions Characteristic 30 TMCL MCLR Pulse Width (low) 2000* — — ns VDD = 5.
PIC12F508/509/16F505 FIGURE 10-7: TIMER0 CLOCK TIMINGS – PIC12F508/509/16F505 T0CKI 40 41 42 TABLE 10-7: TIMER0 CLOCK REQUIREMENTS – PIC12F508/509/16F505 Standard Operating Conditions (unless otherwise specified) Operating Temperature -40°C ≤ TA ≤ +85°C (industrial) -40°C ≤ TA ≤ +125°C (extended) Operating Voltage VDD range is described in Section 10.1 "DC Characteristics" AC CHARACTERISTICS Param Sym No.
PIC12F508/509/16F505 11.0 DC AND AC CHARACTERISTICS GRAPHS AND CHARTS Graphs and charts are not available at this time. © 2005 Microchip Technology Inc.
PIC12F508/509/16F505 NOTES: DS41236B-page 80 Preliminary © 2005 Microchip Technology Inc.
PIC12F508/509/16F505 12.0 PACKAGING INFORMATION 12.1 Package Marking Information 8-Lead PDIP Example 12F508-I /P017 0410 XXXXXXXX XXXXXNNN YYWW 8-Lead SOIC (.150”) Example XXXXXXXX XXXXYYWW NNN 12F509-I /SN0410 017 8-Lead MSOP Example 12F509 0431017 XXXXXX YWWNNN Legend: XX...
PIC12F508/509/16F505 12.1 Package Marking Information (Cont’d) 14-Lead PDIP (300 mil) Example XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN PIC16F505-I/PG 0215 0410017 Example 14-Lead SOIC (150 mil) PIC16F505-E /SLG0125 0431017 XXXXXXXXXXX XXXXXXXXXXX YYWWNNN Example 14-Lead TSSOP (150 mil) 16F505-I 0431 017 XXXXXXXX YYWW NNN DS41236B-page 82 Preliminary © 2005 Microchip Technology Inc.
PIC12F508/509/16F505 8-Lead Plastic Dual In-line (P) – 300 mil (PDIP) E1 D 2 n 1 α E A2 A L c A1 β B1 p eB B Units Dimension Limits n p Number of Pins Pitch Top to Seating Plane Molded Package Thickness Base to Seating Plane Shoulder to Shoulder Width Molded Package Width Overall Length Tip to Seating Plane Lead Thickness Upper Lead Width Lower Lead Width Overall Row Spacing Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic A A2 A1 E E1 D L c §
PIC12F508/509/16F505 8-Lead Plastic Small Outline (SN) – Narrow, 150 mil (SOIC) E E1 p D 2 B n 1 h α 45° c A2 A φ β L Units Dimension Limits n p Number of Pins Pitch Overall Height Molded Package Thickness Standoff § Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic A A2 A1 E E1 D h L φ c B α β MIN .053 .052 .004 .228 .146 .189 .
PIC12F508/509/16F505 8-Lead Plastic Micro Small Outline Package (MS) (MSOP) E E1 p D 2 B n 1 α A2 A c φ A1 (F) L β Units Dimension Limits n p MIN INCHES NOM MAX MILLIMETERS* NOM 8 0.65 BSC 0.75 0.85 0.00 4.90 BSC 3.00 BSC 3.00 BSC 0.40 0.60 0.95 REF 0° 0.08 0.22 5° 5° - MIN 8 Number of Pins Pitch .026 BSC A .043 Overall Height A2 Molded Package Thickness .030 .033 .037 A1 .000 .006 Standoff E Overall Width .193 TYP. E1 .118 BSC Molded Package Width D .118 BSC Overall Length L .016 .024 .
PIC12F508/509/16F505 14-Lead Plastic Dual In-line (P) – 300 mil (PDIP) E1 D 2 n 1 α E A2 A L c A1 β B1 eB p B Units Dimension Limits n p MIN INCHES* NOM 14 .100 .155 .130 MAX MILLIMETERS NOM 14 2.54 3.56 3.94 2.92 3.30 0.38 7.62 7.94 6.10 6.35 18.80 19.05 3.18 3.30 0.20 0.29 1.14 1.46 0.36 0.46 7.87 9.40 5 10 5 10 MIN Number of Pins Pitch Top to Seating Plane A .140 .170 Molded Package Thickness A2 .115 .145 Base to Seating Plane A1 .015 Shoulder to Shoulder Width E .300 .313 .
PIC12F508/509/16F505 14-Lead Plastic Small Outline (SL) – Narrow, 150 mil (SOIC) E E1 p D 2 B n 1 α h 45° c A2 A φ A1 L β Units Dimension Limits n p Number of Pins Pitch Overall Height Molded Package Thickness Standoff § Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic A A2 A1 E E1 D h L φ c B α β MIN .053 .052 .004 .228 .150 .
PIC12F508/509/16F505 14-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP) E E1 p D 2 1 n B α A c φ β A1 L Units Dimension Limits n p Number of Pins Pitch Overall Height Molded Package Thickness Standoff § Overall Width Molded Package Width Molded Package Length Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic A A2 A1 E E1 D L φ c B α β MIN .033 .002 .246 .169 .193 .020 0 .004 .
PIC12F508/509/16F505 APPENDIX A: REVISION HISTORY Revision A (April 2004) Original devices data sheet for PIC12F508/509/16F505 Revision B (June 2005) Update packages © 2005 Microchip Technology Inc.
PIC12F508/509/16F505 NOTES: DS41236B-page 90 Preliminary © 2005 Microchip Technology Inc.
PIC12F508/509/16F505 INDEX A ALU ....................................................................................... 9 Assembler MPASM Assembler..................................................... 64 B Block Diagram On-Chip Reset Circuit ................................................. 47 Timer0......................................................................... 33 TMR0/WDT Prescaler................................................. 37 Watchdog Timer...............................................
PIC12F508/509/16F505 W Wake-up from Sleep ........................................................... 52 Watchdog Timer (WDT) ................................................ 39, 49 Period.......................................................................... 49 Programming Considerations ..................................... 49 WWW Address.................................................................... 93 WWW, On-Line Support........................................................ 3 Z Zero bit ....
PIC12F508/509/16F505 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers.
PIC12F508/509/16F505 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document.
PIC12F508/509/16F505 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO.
WORLDWIDE SALES AND SERVICE AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Web Address: www.microchip.
