Datasheet

PIC16(L)F1946/1947
DS41414D-page 34  2010-2012 Microchip Technology Inc.
Bank 1
080h
(2)
INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory
(not a physical register)
xxxx xxxx xxxx xxxx
081h
(2)
INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory
(not a physical register)
xxxx xxxx xxxx xxxx
082h
(2)
PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000
083h
(2)
STATUS — — —TOPD ZDCC---1 1000 ---q quuu
084h
(2)
FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu
085h
(2)
FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000
086h
(2)
FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu
087h
(2)
FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000
088h
(2)
BSR — — — BSR<4:0> ---0 0000 ---0 0000
089h
(2)
WREG Working Register 0000 0000 uuuu uuuu
08Ah
(1, 2)
PCLATH — Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000
08Bh
(2)
INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 000x 0000 000u
08Ch TRISA PORTA Data Direction Register 1111 1111 1111 1111
08Dh TRISB PORTB Data Direction Register 1111 1111 1111 1111
08Eh TRISC PORTC Data Direction Register 1111 1111 1111 1111
08Fh TRISD PORTD Data Direction Register 1111 1111 1111 1111
090h TRISE PORTE Data Direction Register 1111 1111 1111 1111
091h PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
092h PIE2 OSFIE C2IE C1IE EEIE BCLIE LCDIE C3IE CCP2IE 0000 0000 0000 0000
093h PIE3
— CCP5IE CCP4IE CCP3IE TMR6IE —TMR4IE— -000 0-0- -000 0-0-
094h PIE4
— — RC2IE TX2IE — — BCL2IE SSP2IE --00 --00 --00 --00
095h OPTION_REG WPUEN
INTEDG T0CS T0SE PSA PS<2:0> 1111 1111 1111 1111
096h PCON STKOVF STKUNF
— —RMCLRRI POR BOR 00-- 11qq qq-- qquu
097h WDTCON
— — WDTPS<4:0> SWDTEN --01 0110 --01 0110
098h OSCTUNE
— —TUN<5:0>--00 0000 --00 0000
099h OSCCON SPLLEN IRCF<3:0>
—SCS<1:0>0011 1-00 0011 1-00
09Ah OSCSTAT T1OSCR PLLR OSTS HFIOFR HFIOFL MFIOFR LFIOFR
HFIOFS 00q0 0q0- qqqq qq0-
09Bh ADRESL A/D Result Register Low xxxx xxxx uuuu uuuu
09Ch ADRESH A/D Result Register High xxxx xxxx uuuu uuuu
09Dh ADCON0
— CHS<4:0> GO/DONE ADON -000 0000 -000 0000
09Eh ADCON1 ADFM ADCS<2:0>
— ADNREF ADPREF1 ADPREF0 0000 -000 0000 -000
09Fh
— Unimplemented — —
TABLE 3-10: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Value on all
other
Resets
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are
transferred to the upper byte of the program counter.
2: These registers can be addressed from any bank.
3: Unimplemented, read as ‘1’.