Datasheet

 2010-2012 Microchip Technology Inc. DS41414D-page 253
PIC16(L)F1946/47
24.2.6 SPI OPERATION IN SLEEP MODE
In SPI Master mode, module clocks may be operating
at a different speed than when in full power mode; in
the case of the Sleep mode, all clocks are halted.
Special care must be taken by the user when the
MSSPx clock is much faster than the system clock.
In Slave mode, when MSSPx interrupts are enabled,
after the master completes sending data, an MSSPx
interrupt will wake the controller from Sleep.
If an exit from Sleep mode is not desired, MSSPx inter-
rupts should be disabled.
In SPI Master mode, when the Sleep mode is selected,
all module clocks are halted and the transmis-
sion/reception will remain in that state until the device
wakes. After the device returns to Run mode, the mod-
ule will resume transmitting and receiving data.
In SPI Slave mode, the SPI Transmit/Receive Shift
register operates asynchronously to the device. This
allows the device to be placed in Sleep mode and data
to be shifted into the SPI Transmit/Receive Shift
register. When all 8 bits have been received, the
MSSPx interrupt flag bit will be set and if enabled, will
wake the device.
TABLE 24-1: SUMMARY OF REGISTERS ASSOCIATED WITH SPI OPERATION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Register
on Page
ANSELA
ANSA7 ANSA6 ANSA5 ANSA4 ANSA3 ANSA2 ANSA1 ANSA0
132
APFCON
P3CSEL P3BSEL P2DSEL P2CSEL P2BSEL CCP2SEL P1CSEL P1BSEL
129
INTCON GIE PEIE
TMR0IE INTE IOCIE TMR0IF INTF IOCIF
92
PIE1
TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE
93
PIE4
— — RC2IE TX2IE — — BCL2IE SSP2IE
96
PIR1
TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF
97
PIR4
— — RC2IF TX2IF — — BCL2IF SSP2IF
100
SSP1BUF
Synchronous Serial Port Receive Buffer/Transmit Register
247*
SSP2BUF
Synchronous Serial Port Receive Buffer/Transmit Register
247*
SSP1CON1 WCOL SSPOV SSPEN CKP SSPM<3:0>
292
SSP1CON3
ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN
295
SSP1STAT SMP CKE
D/A P S R/W UA BF 291
SSP2CON1 WCOL SSPOV SSPEN CKP SSPM<3:0>
292
SSP2CON3
ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN
295
SSP2STAT SMP CKE
D/A P S R/W UA BF 291
TRISA
TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0
131
TRISB
TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0
134
Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by the MSSPx in SPI mode.
* Page provides register information.