Datasheet

 2010-2012 Microchip Technology Inc. DS41414D-page 135
PIC16(L)F1946/47
TABLE 12-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
REGISTER 12-9: WPUB: WEAK PULL-UP PORTB REGISTER
R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1
WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-0 WPUB<7:0>: Weak Pull-up Register bits
1 = Pull-up enabled
0 = Pull-up disabled
Note 1: Global WPUEN
bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled.
2: The weak pull-up device is automatically disabled if the pin is in configured as an output.
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Register
on Page
INTCON
GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 92
IOCBP IOCBP7 IOCBP6 IOCBP5 IOCBP4 IOCBP3 IOCBP2 IOCBP1 IOCBP0 155
IOCBN IOCBN7 IOCBN6 IOCBN5 IOCBN4 IOCBN3 IOCBN2 IOCBN1 IOCBN0 155
IOCBF IOCBF7 IOCBF6 IOCBF5 IOCBF4 IOCBF3 IOCBF2 IOCBF1 IOCBF0 155
LATB LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 134
LCDSE1
SE15 SE14 SE13 SE12 SE11 SE10 SE9 SE8 341
LCDSE3
SE31 SE30 SE29 SE28 SE27 SE26 SE25 SE24 341
LCDSE4 SE39 SE38
SE37 SE36 SE35 SE34 SE33 SE32 341
OPTION_REG WPUEN
INTEDG TMR0CS TMR0SE PSA PS<2:0> 197
PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 134
T1GCON TMR1GE
T1GPOL T1GTM T1GSPM T1GGO/DONE T1GVAL T1GSS<1:0> 208
TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 134
WPUB WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 135
Legend: x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by PORTB.