Datasheet
PIC16(L)F1946/47
DS41414D-page 132 2010-2012 Microchip Technology Inc.
TABLE 12-3: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
TABLE 12-4: SUMMARY OF CONFIGURATION WORD WITH PORTA
REGISTER 12-5: ANSELA: PORTA ANALOG SELECT REGISTER
U-0 U-0 R/W-1/1 U-0 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1
— — ANSA5 — ANSA3 ANSA2 ANSA1 ANSA0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-6 Unimplemented: Read as ‘0’
bit 5 ANSA5: Analog Select between Analog or Digital Function on pins RA<5>, respectively
0 = Digital I/O. Pin is assigned to port or digital special function.
1 = Analog input. Pin is assigned as analog input
(1)
. Digital input buffer disabled.
bit 4 Unimplemented: Read as ‘0’
bit 3-0 ANSA<3:0>: Analog Select between Analog or Digital Function on pins RA<3:0>, respectively
0 = Digital I/O. Pin is assigned to port or digital special function.
1 = Analog input. Pin is assigned as analog input
(1)
. Digital input buffer disabled.
Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to
allow external control of the voltage on the pin.
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Register
on Page
ADCON0
— CHS<4:0>
GO/DONE
ADON
168
ADCON1
ADFM ADCS<2:0> — — ADPREF<1:0>
169
ANSELA
— —ANSA5— ANSA3 ANSA2 ANSA1 ANSA0
132
CPSCON0 CPSON
CPSRM — — CPSRNG1 CPSRNG0 CPSOUT T0XCS 333
CPSCON1
— — — CPSCH<4:0>
334
DACCON0 DACEN
DACLPS DACOE --- DACPSS<1:0> --- DACNSS
178
LATA LATA7 LATA6 LATA5 LATA4 LATA3 LATA2 LATA1 LATA0
131
LCDSE1 SE15 SE14
SE13 SE12 SE11 SE10 SE9 SE8 341
LCDSE2
SE23 SE22 SE21 SE20 SE19 SE18 SE17 SE16 341
LCDSE4
SE39 SE38 SE37 SE36 SE35 SE34 SE33 SE32 341
OPTION_REG
WPUEN INTEDG TMR0CS TMR0SE PSA PS<2:0>
197
PORTA RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0
131
TRISA TRISA7TRISA6TRISA5TRISA4TRISA3TRISA2TRISA1TRISA0
131
Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA.
Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0
Register
on Page
CONFIG1
13:8
— — FCMEN IESO CLKOUTEN BOREN<1:0> CPD
56
7:0
CP MCLRE PWRTE WDTE<1:0> FOSC<2:0>
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by PORTA.