Datasheet

PIC16(L)F1946/1947
DS41414D-page 36  2010-2012 Microchip Technology Inc.
Bank 3
180h
(2)
INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory
(not a physical register)
xxxx xxxx xxxx xxxx
181h
(2)
INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory
(not a physical register)
xxxx xxxx xxxx xxxx
182h
(2)
PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000
183h
(2)
STATUS — — —TOPD ZDCC---1 1000 ---q quuu
184h
(2)
FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu
185h
(2)
FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000
186h
(2)
FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu
187h
(2)
FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000
188h
(2)
BSR — — — BSR<4:0> ---0 0000 ---0 0000
189h
(2)
WREG Working Register 0000 0000 uuuu uuuu
18Ah
(1, 2)
PCLATH — Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000
18Bh
(2)
INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 000x 0000 000u
18Ch ANSELA
— — ANSA5 — ANSA3 ANSA2 ANSA1 ANSA0 --1- 1111 --1- 1111
18Dh
— Unimplemented — —
18Eh
— Unimplemented — —
18Fh
— Unimplemented — —
190h ANSELE
— — — — — ANSE2 ANSE1 ANSE0 ---- -111 ---- -111
191h EEADRL EEPROM / Program Memory Address Register Low Byte 0000 0000 0000 0000
192h EEADRH
—
(3)
EEPROM / Program Memory Address Register High Byte 1000 0000 1000 0000
193h EEDATL EEPROM / Program Memory Read Data Register Low Byte xxxx xxxx uuuu uuuu
194h EEDATH
— — EEPROM / Program Memory Read Data Register High Byte --xx xxxx --uu uuuu
195h EECON1 EEPGD CFGS LWLO FREE WRERR WREN WR RD 0000 x000 0000 q000
196h EECON2 EEPROM control register 2 0000 0000 0000 0000
197h
— Unimplemented — —
198h
— Unimplemented — —
199h RC1REG USART Receive Data Register 0000 0000 0000 0000
19Ah TX1REG USART Transmit Data Register 0000 0000 0000 0000
19Bh SP1BRGL EUSART1 Baud Rate Generator, Low Byte 0000 0000 0000 0000
19Ch SP1BRGH EUSART1 Baud Rate Generator, High Byte 0000 0000 0000 0000
19Dh RC1STA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
19Eh TX1STA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010
19Fh BAUD1CON ABDOVF RCIDL
— SCKP BRG16 — WUE ABDEN 01-0 0-00 01-0 0-00
TABLE 3-10: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Value on all
other
Resets
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are
transferred to the upper byte of the program counter.
2: These registers can be addressed from any bank.
3: Unimplemented, read as ‘1’.