Datasheet

 2008-2011 Microchip Technology Inc. DS41364E-page 107
PIC16(L)F1934/6/7
8.0 LOW DROPOUT (LDO)
VOLTAGE REGULATOR
The PIC16F1934/6/7 has an internal Low Dropout
Regulator (LDO) which provides operation above 3.6V.
The LDO regulates a voltage for the internal device
logic while permitting the V
DD and I/O pins to operate
at a higher voltage. There is no user enable/disable
control available for the LDO, it is always active. The
PIC16(L)F1934/6/7 operates at a maximum V
DD of
3.6V and does not incorporate an LDO.
A device I/O pin may be configured as the LDO voltage
output, identified as the V
CAP pin. Although not
required, an external low-ESR capacitor may be con-
nected to the VCAP pin for additional regulator stability.
The VCAPEN<1:0> bits of Configuration Word 2 deter-
mines which pin is assigned as the V
CAP pin. Refer to
Table 8-1.
On power-up, the external capacitor will load the LDO
voltage regulator. To prevent erroneous operation, the
device is held in Reset while a constant current source
charges the external capacitor. After the cap is fully
charged, the device is released from Reset. For more
information on recommended capacitor values and the
constant current rate, refer to the LDO Regulator
Characteristics Table in the applicable Electrical
Specifications Chapter.
TABLE 8-2: SUMMARY OF CONFIGURATION WORD WITH LDO
TABLE 8-1: VCAPEN<1:0> SELECT BITS
VCAPEN<1:0> Pin
00 RA0
01 RA5
10 RA6
11 No Vcap
Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0
Register
on Page
CONFIG2
13:8
— — LVP DEBUG — BORV STVREN PLLEN
64
7:0
— —
VCAPEN1
(1)
VCAPEN0
(1)
— — WRT1 WRT0
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used by LDO.
Note 1: PIC16F1934/6/7 only.