Datasheet

PIC16F193X/LF193X
DS41364D-page 446 Preliminary 2009 Microchip Technology Inc.
31.1 DC Characteristics: PIC16F/LF1938/39-I/E (Industrial, Extended)
PIC16LF1938/39
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
-40°C T
A +125°C for extended
PIC16F1938/39
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C T
A +85°C for industrial
-40°C T
A +125°C for extended
Param.
No.
Sym. Characteristic Min. Typ† Max. Units Conditions
D001 V
DD Supply Voltage
PIC16LF1938/39 1.8
2.3
3.6
3.6
V
V
F
OSC 16 MHz:
F
OSC 32 MHz (NOTE 2)
D001 PIC16F1938/39 1.8
2.3
5.5
5.5
V
V
FOSC 16 MHz:
F
OSC 32 MHz (NOTE 2)
D002* V
DR RAM Data Retention Voltage
(1)
PIC16LF1938/39 1.5 V Device in Sleep mode
D002* PIC16F1938/39 1.7 V Device in Sleep mode
V
POR* Power-on Reset Release Voltage —1.6 V
V
PORR* Power-on Reset Rearm Voltage
PIC16LF1938/39 0.8 V Device in Sleep mode
PIC16F1938/39 1.7 V Device in Sleep mode
D003 V
ADFVR Fixed Voltage Reference Voltage
for ADC, Initial Accuracy
-6
-7
-7
-8
-7
-8
4
4
6
6
4
4
% 1.024V, V
DD 1.8V, 85°C
1.024V, V
DD 1.8V, 125°C
2.048V, V
DD 2.5V, 85°C
2.048V, V
DD 2.5V, 125°C
4.096V, V
DD 4.75V, 85°C
4.096V, V
DD 4.75V, 125°C
D003A V
CDAFVR Fixed Voltage Reference Voltage
for Comparator and DAC, Initial
Accuracy
-7
-8
-8
-9
-8
-8
5
5
7
7
4
4
% 1.024V, V
DD 1.8V, 85°C
1.024V, V
DD 1.8V, 125°C
2.048V, V
DD 2.5V, 85°C
2.048V, V
DD 2.5V, 125°C
4.096V, V
DD 4.75V, 85°C
4.096V, V
DD 4.75V, 125°C
D003B V
LCDFVR Fixed Voltage Reference Voltage
for LCD Bias, Initial Accuracy
-9
-9.5
9
9
% 3.072V, VDD 3.6V, 85°C
3.072V, V
DD 3.6V, 125°C
D003C* TCV
FVR Temperature Coefficient, Fixed
Voltage Reference
-130 ppm/°C
D003D* V
FVR/
V
IN
Line Regulation, Fixed Voltage Ref-
erence
0.270 %/V
D004* S
VDD VDD Rise Rate to ensure internal
Power-on Reset signal
0.05 V/ms See Section 6.1 “Power-on Reset
(POR)” for details.
* These parameters are characterized but not tested.
Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.
2: PLL required for 32 MHz operation.