Datasheet

ManualsBrandsMICROCHIP TECHNOLOGY ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller SSOP 28 8-Bit 32 MHz I/O number 25

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PIC16(L)F1934/6/7

DS41364E-page 190  2008-2011 Microchip Technology Inc.

TABLE 19-2: SUMMARY OF REGISTERS ASSOCIATED WITH SR LATCH MODULE

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0

SRSPE SRSCKE SRSC2E SRSC1E SRRPE SRRCKE SRRC2E SRRC1E

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 SRSPE: SR Latch Peripheral Set Enable bit

1 = SR Latch is set when the SRI pin is high.

0 = SRI pin has no effect on the set input of the SR Latch

bit 6 SRSCKE: SR Latch Set Clock Enable bit

1 = Set input of SR Latch is pulsed with SRCLK

0 = SRCLK has no effect on the set input of the SR Latch

bit 5 SRSC2E: SR Latch C2 Set Enable bit

1 = SR Latch is set when the C2 Comparator output is high

0 = C2 Comparator output has no effect on the set input of the SR Latch

bit 4 SRSC1E: SR Latch C1 Set Enable bit

1 = SR Latch is set when the C1 Comparator output is high

0 = C1 Comparator output has no effect on the set input of the SR Latch

bit 3 SRRPE: SR Latch Peripheral Reset Enable bit

1 = SR Latch is reset when the SRI pin is high.

0 = SRI pin has no effect on the reset input of the SR Latch

bit 2 SRRCKE: SR Latch Reset Clock Enable bit

1 = Reset input of SR Latch is pulsed with SRCLK

0 = SRCLK has no effect on the reset input of the SR Latch

bit 1 SRRC2E: SR Latch C2 Reset Enable bit

1 = SR Latch is reset when the C2 Comparator output is high

0 = C2 Comparator output has no effect on the reset input of the SR Latch

bit 0 SRRC1E: SR Latch C1 Reset Enable bit

1 = SR Latch is reset when the C1 Comparator output is high

0 = C1 Comparator output has no effect on the reset input of the SR Latch

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

on Page

ANSELA

— — ANSA5 ANSA4 ANSA3 ANSA2 ANSA1 ANSA0

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SRCON0 SRLEN SRCLK<2:0> SRQEN SRNQEN SRPS SRPR 189

SRCON1 SRSPE SRSCKE SRSC2E SRSC1E SRRPE SRRCKE SRRC2E SRRC1E 190

TRISA

TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0

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Legend: — = unimplemented location, read as ‘0’. Shaded cells are unused by the SR Latch module.