Datasheet

 2009-2012 Microchip Technology Inc. DS80490L-page 9
PIC16(L)F1933
FIGURE 1: INSTRUCTION CYCLE DELAY CALCULATION EXAMPLE
In Figure 1, 88 instruction cycles (TCY) will be
required to complete the full conversion. Each T
AD
cycle consists of 8 TCY periods. A fixed delay is
provided to stop the A/D conversion after 86
instruction cycles and terminate the conversion at
the correct time as shown in the figure above.
EXAMPLE 3: CODE EXAMPLE OF
INSTRUCTION CYCLE
DELAY
For other combinations of FOSC, TAD values and
Instruction cycle delay counts, refer to Tabl e 4.
TABLE 4: INSTRUCTION CYCLE DELAY
COUNTS BY T
AD SELECTION
Affected Silicon Revisions
FOSC = 32 MHz
TCY = 4/32 MHz = 125 nsec
TAD = 1 µsec, ADCS = FOSC/32
88 TCY
84 TCY
8 TCY
4 TCY
1 TAD
11 TAD
Stop the A/D conversion
between 10.5 and 11 T
AD
cycles.
See the Analog-to-Digital
Conversion Timing diagram
in the Analog-to-Digital
Converter chapter of the
device data sheet.
}
See the ADC Clock Period (TAD) vs. Device Operating Frequencies table, in the Analog-to-Digital Converter
section of the device data sheet.
Note: The exact delay time will depend on the
T
AD divisor (ADCS) selection. The TCY
counts shown in the timing diagram above
apply to this example only. Refer to
Table 4 for the required delay counts for
other configurations.
BSF ADCON0, ADGO ; Start ADC conversion
; Provide 86
instruction cycle
delay here
BCF ADCON0, ADGO ; Terminate the
conversion manually
MOVF ADRESH, W ; Read conversion
result
TAD Instruction Cycle Delay Counts
F
OSC/64 172
FOSC/32 86
F
OSC/16 43
A1 A2 A3 A4 A6 A7 A8
X X X