Datasheet

PIC16(L)F1933
DS80490L-page 8  2009-2012 Microchip Technology Inc.
6. Module: Resets
6.1 Reset under Low-Power Conditions
This issue pertains to the PIC16F1933 product
only. The PIC16LF1933 product is not affected by
this issue in any way.
When employing any one of the low-power
oscillators, (ECL mode, LP Mode, LFINTOSC, or
Timer1 Oscillator) while, at the same time, the
source voltage supplied to the V
DD pin drops
below 2.7 volts, the device will experience a
Power-on Reset (POR).
Also, when the source voltage supplied to the V
DD
pin is below 2.7 volts and a SLEEP instruction is
executed, the device will experience a Power-on
Reset (POR) upon entering Sleep mode,
regardless of the type of clock source being used
or which power-managed mode is being
employed.
Work around
There are three separate work-arounds available
to avoid this Reset condition. Employing any one
of these work-arounds will avoid this Reset
condition.
• Enabling the Brown-out Reset (BOR) circuitry.
• Enabling the Fixed Voltage Reference (FVR)
module.
• Maintaining a source voltage (V
DD) to the
device above 2.7 volts.
The ‘Affected Silicon Revisions’ below refers
only to PIC16F1933.
Affected Silicon Revisions
7. Module: ADC
7.1 Analog-to-Digital Conversion
An ADC conversion may not complete under these
conditions:
1. When F
OSC is greater than 8 MHz and it is the
clock source used for the ADC converter.
2. The ADC is operating from its dedicated internal
FRC oscillator and the device is not in Sleep
mode (any F
OSC frequency).
When this occurs, the ADC Interrupt Flag (ADIF)
does not get set, the GO/DONE
bit does not get
cleared, and the conversion result does not get
loaded into the ADRESH and ADRESL result
registers.
Work around
Method 1: Select the system clock, FOSC, as
the ADC clock source and reduce
the F
OSC frequency to 8 MHz or
less when performing ADC
conversions.
Method 2: Select the dedicated FRC
oscillator as the ADC conversion
clock source and perform all
conversions with the device in
Sleep.
Method 3: This method is provided if the
application cannot use Sleep
mode and requires continuous
operation at frequencies above 8
MHz. This method requires early
termination of an ADC
conversion. Provide a fixed time
delay in software to stop the A-to-
D conversion manually, after all
10 bits are converted, but before
the conversion would complete
automatically. The conversion is
stopped by clearing the GO/
DONE
bit in software. The GO/
DONE
bit must be cleared during
the last ½ T
AD cycle, before the
conversion would have
completed automatically. Refer to
Figure 1 for details.
A1 A2 A3 A4 A6 A7 A8
X X