Datasheet

PIC16(L)F1933
DS80490L-page 4  2009-2012 Microchip Technology Inc.
Silicon Errata Issues
1. Module: Data EE Memory
1.1 Data EE Memory Endurance
The typical write/erase endurance of the Data EE
Memory is limited to 10k cycles.
Work around
Use error correction method that stores data in
multiple locations.
Affected Silicon Revisions
1.2 Data EE Write at Min. VDD
The minimum voltage required for a Data EE write
operation is 2.0 volts.
Work around
None.
Affected Silicon Revisions
2. Module: Program Flash Memory (PFM)
2.1 Program Flash Memory Endurance
The typical write/erase endurance of the PFM is
limited to 1k cycles when V
DD is above 3.0 volts.
Work around
Use an error correction method that stores data
in multiple locations.
Affected Silicon Revisions
2.2 Program Flash Memory writes at Min. VDD
The minimum voltage required for a PFM write
operation is 2.0V.
Work around
None.
Affected Silicon Revisions
3. Module: Timer1
3.1 Timer1 Gate Toggle mode with Timer0 as
Gate Source
Timer1 Gate Toggle mode provides unexpected
results when Timer0 overflow is selected as the
Timer1 gate source. We do not recommend using
Timer0 overflow as the Timer1 gate source while
in Timer1 Gate Toggle mode or when Toggle
mode is used in conjunction with Timer1 Gate
Single-Pulse mode.
Work around
None.
Affected Silicon Revisions
3.2 Timer1 Gate Toggle mode
When Timer1 Gate Toggle mode is enabled, it is
possible to measure the full-cycle length of a
Timer1 gate signal. To perform this function, the
Timer1 gate source is routed through a flip-flop
that changes state on every incrementing edge of
the gate signal. Timer1 Gate Toggle mode is
enabled by setting the T1GTM bit of the T1GCON
register. When working properly, clearing either
the T1GTM bit or the TMR1ON bit would also clear
the output value of this flip-flop, and hold it clear.
This is done in order to control which edge is being
measured. The issue that exists is that clearing the
TMR1ON bit does not clear the output value of the
flip-flop and hold it clear.
Work around
Clear the T1GTM bit in the T1GCON register to
clear and hold clear the output value of the flip-flop.
Affected Silicon Revisions
Note: This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated by the shaded column in
the following tables apply to the current
silicon revision (A8).
A1 A2 A3 A4 A6 A7 A8
X
A1 A2 A3 A4 A6 A7 A8
X X XXX X X
A1 A2 A3 A4 A6 A7 A8
X
A1 A2 A3 A4 A6 A7 A8
X X XXX X X
A1 A2 A3 A4 A6 A7 A8
X X
A1 A2 A3 A4 A6 A7 A8
X X X